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1. (WO2019009208) HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING SAME
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Pub. No.: WO/2019/009208 International Application No.: PCT/JP2018/024868
Publication Date: 10.01.2019 International Filing Date: 29.06.2018
IPC:
H05K 3/46 (2006.01) ,C04B 35/16 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/13 (2006.01) ,H01L 23/36 (2006.01) ,H05K 1/03 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
C CHEMISTRY; METALLURGY
04
CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
B
LIME; MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
35
Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
01
based on oxides
16
based on silicates other than clay
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
03
Use of materials for the substrate
Applicants:
TDK株式会社 TDK CORPORATION [JP/JP]; 東京都中央区日本橋二丁目5番1号 2-5-1, Nihonbashi, Chuo-ku, Tokyo 1036128, JP
Inventors:
仁宮 恵美 NINOMIYA Emi; JP
▲高▼橋 真由美 TAKAHASHI Mayumi; JP
Agent:
棚井 澄雄 TANAI Sumio; JP
荒 則彦 ARA Norihiko; JP
飯田 雅人 IIDA Masato; JP
荻野 彰広 OGINO Akihiro; JP
Priority Data:
2017-13030403.07.2017JP
Title (EN) HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING SAME
(FR) SUBSTRAT DE DISSIPATION DE CHALEUR ET PROCÉDÉ DE PRODUCTION ASSOCIÉ
(JA) 放熱基板及びその製造方法
Abstract:
(EN) This heat dissipation substrate (100) comprises a plurality of conductor pattern layers (4, 4A-4D); and an electronic component is mounted on this heat dissipation substrate. This heat dissipation substrate is provided with a plurality of core materials (10, 10A-10C) which contain a ceramic material; at least one of the plurality of core materials (10A-10C), namely a core material (10A) is provided with conductor pattern layers (4A, 4B) on a first surface (10Aa) and a second surface (10Ab); and this heat dissipation substrate is obtained by laminating the plurality of core material layers (10A-10C), with resin layers (2, 2A, 2B) being interposed therebetween.
(FR) L'invention concerne un substrat de dissipation de chaleur (100) comprenant une pluralité de couches de motif conducteur (4, 4A-4D) ; et un composant électronique est monté sur ce substrat de dissipation de chaleur. Ce substrat de dissipation de chaleur est doté d'une pluralité de matériaux de noyau (10, 10A-10C) qui contiennent un matériau céramique ; au moins l'un de la pluralité de matériaux de noyau (10A-10C), à savoir un matériau de noyau (10A), est doté de couches de motif conducteur (4A, 4B) sur une première surface (10Aa) et une seconde surface (10Ab) ; et ce substrat de dissipation de chaleur est obtenu par la stratification de la pluralité de couches de matériau de noyau (10A-10C), des couches de résine (2, 2A, 2B) étant interposées entre ces dernières.
(JA) 放熱基板(100)は、複数の導体パターン層(4、4A~4D)を有し、電子部品が実装される放熱基板であって、セラミック材料を含有する複数のコア材(10、10A~10C)を備え、複数のコア材(10A~10C)のうちの少なくとも一部のコア材であるコア材(10A)は、第1面(10Aa)及び第2面(10Ab)に導体パターン層(4A、4B)が形成されており、複数のコア材層(10A~10C)が樹脂層(2、2A、2B)を介して積層されてなる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)