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1. (WO2019009167) THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE
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Pub. No.: WO/2019/009167 International Application No.: PCT/JP2018/024480
Publication Date: 10.01.2019 International Filing Date: 28.06.2018
IPC:
H01L 29/786 (2006.01) ,G02F 1/1345 (2006.01) ,G02F 1/1368 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1345
Conductors connecting electrodes to cell terminals
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
川崎 達也 KAWASAKI, Tatsuya; --
北川 英樹 KITAGAWA, Hideki; --
原 義仁 HARA, Yoshihito; --
前田 昌紀 MAEDA, Masaki; --
伊藤 俊克 ITOH, Toshikatsu; --
今井 元 IMAI, Hajime; --
大東 徹 DAITOH, Tohru; --
Agent:
特許業務法人 安富国際特許事務所 YASUTOMI & ASSOCIATES; 大阪府大阪市淀川区宮原3丁目5番36号 5-36, Miyahara 3-chome, Yodogawa-ku, Osaka-shi, Osaka 5320003, JP
Priority Data:
2017-13193805.07.2017JP
Title (EN) THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE
(FR) SUBSTRAT DE MATRICE À TRANSISTORS À COUCHE MINCE ET DISPOSITIF D’AFFICHAGE
(JA) 薄膜トランジスタアレイ基板及び表示装置
Abstract:
(EN) The present invention provides a thin-film transistor array substrate with which, even when frame size is reduced, step disconnection of a semiconductor layer of a thin-film transistor element can be prevented. The thin-film transistor array substrate of the present invention is a thin-film transistor array substrate in which a pixel region is provided with a thin-film transistor element, and a terminal region is provided with a terminal. In a cross sectional view of the pixel region, a support base material, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer are arranged in order. In a plan view of the pixel region, a region in which the insulating layer is arranged includes a region in which the semiconductor layer is arranged. In a cross sectional view of the terminal region, the support base material, a lead-out wire led out from the terminal, and the insulating layer are arranged in order.
(FR) La présente invention concerne un substrat de matrice à transistors à couche mince grâce auquel, même lorsque la taille d’armature est réduite, la déconnexion pas-à-pas d’une couche semi-conductrice d’un élément de transistor à couche mince peut être évitée. Le substrat de matrice à transistors à couche mince selon la présente invention est un substrat de matrice à transistors à couche mince dans lequel une zone de pixels comporte un élément de transistor à couche mince, et une zone de borne comporte une borne. Dans une vue en section transversale de la zone de pixels, un matériau de base de support, une couche isolante, une électrode de grille, une couche isolante de grille, et une couche semi-conductrice sont agencés dans cet ordre. Dans une vue planaire de la zone de pixels, une zone dans laquelle est agencée la couche isolante inclut une zone dans laquelle est agencée la couche semi-conductrice. Dans une vue en section transversale de la zone de borne, le matériau de base de support, un câble de sortie sortant de la borne, et la couche isolante sont agencés dans cet ordre.
(JA) 本発明は、狭額縁化を図る場合であっても薄膜トランジスタ素子の半導体層の段切れが防止される薄膜トランジスタアレイ基板を提供する。本発明の薄膜トランジスタアレイ基板は、画素領域に薄膜トランジスタ素子を備え、かつ、端子領域に端子を備える薄膜トランジスタアレイ基板であって、上記画素領域の断面視において、支持基材と、絶縁層と、ゲート電極と、ゲート絶縁層と、半導体層とが順に配置され、上記画素領域の平面視において、上記絶縁層の配置領域は、上記半導体層の配置領域を包含し、上記端子領域の断面視において、上記支持基材と、上記端子から導出される引き出し配線と、上記絶縁層とが順に配置されているものである。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)