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1. (WO2019008672) PLL CIRCUIT
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Pub. No.: WO/2019/008672 International Application No.: PCT/JP2017/024498
Publication Date: 10.01.2019 International Filing Date: 04.07.2017
IPC:
H03L 7/197 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18
using a frequency divider or counter in the loop
197
a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
堤 恒次 TSUTSUMI, Koji; JP
柳原 裕貴 YANAGIHARA, Yuki; JP
下澤 充弘 SHIMOZAWA, Mitsuhiro; JP
Agent:
田澤 英昭 TAZAWA, Hideaki; JP
濱田 初音 HAMADA, Hatsune; JP
中島 成 NAKASHIMA, Nari; JP
坂元 辰哉 SAKAMOTO, Tatsuya; JP
辻岡 将昭 TSUJIOKA, Masaaki; JP
井上 和真 INOUE, Kazuma; JP
Priority Data:
Title (EN) PLL CIRCUIT
(FR) CIRCUIT PLL
(JA) PLL回路
Abstract:
(EN) According to the present invention, a phase frequency comparator (4) compares a reference signal with an output signal of a variable frequency divider (3), and outputs a frequency UP signal and a frequency DOWN signal according to the comparison result. An AND circuit (9) performs a logical operation on the UP signal and the DOWN signal, and outputs an operation result as a retiming signal CLKretime. A flip-flop circuit (10) holds and outputs an output signal of a frequency control circuit (8) at a timing which is the same as the timing of an output signal of the AND circuit (9). A ΔΣ modulator (7) determines the frequency division ratio of the variable frequency divider (3) corresponding to the output of the flip-flop circuit (10).
(FR) Selon la présente invention, un comparateur de fréquence de phase (4) compare un signal de référence avec un signal de sortie d'un diviseur de fréquence variable (3), et émet un signal UP de fréquence et un signal DOWN de fréquence selon le résultat de comparaison. Un circuit ET (9) effectue une opération logique sur le signal UP et le signal DOWN, et émet un résultat d'opération sous la forme d'un signal de resynchronisation CLKretime. Un circuit à bascule (10) maintient et énet un signal de sortie d'un circuit de commande de fréquence (8) à une synchronisation qui est la même que la synchronisation d'un signal de sortie du circuit ET (9). Un modulateur ΔΣ (7) détermine le rapport de division de fréquence du diviseur de fréquence variable (3) correspondant à la sortie du circuit à bascule (10).
(JA) 位相周波数比較器(4)は、基準信号と可変分周器(3)の出力信号とを比較し、比較結果に応じた周波数のアップ信号とダウン信号を出力する。アンド回路(9)は、アップ信号とダウン信号との論理積演算を行い、演算結果をリタイミング用信号CLKretimeとして出力する。フリップフロップ回路(10)は、周波数制御回路(8)の出力信号をアンド回路(9)の出力信号のタイミングで保持して出力する。ΔΣ変調器(7)は、フリップフロップ回路(10)の出力に対応して可変分周器(3)の分周比を決定する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)