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1. (WO2019007624) TOLERANCE COMPENSTATION ELEMENT FOR CIRCUIT CONFIGURATIONS
Latest bibliographic data on file with the International Bureau    Submit observation
Pub. No.: WO/2019/007624 International Application No.: PCT/EP2018/064983
Publication Date: 10.01.2019 International Filing Date: 07.06.2018
IPC:
H05K 1/18 (2006.01) ,H01L 23/00 (2006.01) ,H05K 3/34 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
18
Printed circuits structurally associated with non-printed electric components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
34
by soldering
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
SIEMENS AKTIENGESELLSCHAFT [DE/DE]; Werner-von-Siemens-Straße 1 80333 München, DE
Inventors:
KNOFE, Rüdiger; DE
MÜLLER, Bernd; DE
STROGIES, Jörg; DE
WILKE, Klaus; DE
BLANK, Rene; DE
FRANKE, Martin; DE
FRÜHAUF, Peter; DE
NERRETER, Stefan; DE
Priority Data:
10 2017 211 330.804.07.2017DE
Title (EN) TOLERANCE COMPENSTATION ELEMENT FOR CIRCUIT CONFIGURATIONS
(FR) ÉLÉMENT DE COMPENSATION DE TOLÉRANCES POUR SCHÉMAS DE CONNEXIONS
(DE) TOLERANZAUSGLEICHSELEMENT FÜR SCHALTBILDER
Abstract:
(EN) The invention relates to a tolerance compensation element for circuit configurations having a DCB (direct copper bonded) substrate (1) and a PCB (printed circuit board) (2) and to a circuit configuration having said tolerance compensation element. The invention is characterized in that a tolerance compensation element is positioned in a targeted manner between the DCB substrate (1) and PCB (2) in a gap A (3) for the contact-connection of components (5) on the DCB substrate (1) by means of additive manufacturing and is formed so as to close the gap.
(FR) L’invention concerne un élément de compensation de tolérances destiné à des schémas de connexions comprenant un substrat DCB (Direct Copper Bonded) (1) et une carte de circuit imprimé PCB (Printed Circuit Board) (2) et un schéma de connexions pourvu de cet élément de compensation de tolérance. L’invention est caractérisé en ce qu’un élément de compensation de tolérance est inséré de manière ciblée entre le substrat DCB (1) et la carte de circuit imprimé PCB (2) dans un intervalle A (3) pour la mise en contact de composants (5) sur le substrat DCB (1) par fabrication additive et est conçu pour fermer l’intervalle.
(DE) Toleranzausgleichselement für Schaltbilder Die Erfindung betrifft ein Toleranzausgleichselement für Schaltbilder mit einem DCB (Direct Copper Bonded)- Substrat (1) und einer PCB (Printed Circuit Board)-Leiterplatte (2) sowie ein Schaltbild mit diesem Toleranzausgleichselement. Die Erfindung zeichnet sich dadurch aus, dass ein Toleranzausgleichselement zwischen DCB-Substrat (1) und PCB-Leiterplatte (2) in einem Spalt A (3) für die Kontaktierung von Bauelementen (5) auf dem DCB-Substrat (1) mittels Additive Manufacturing gezielt eingestellt ist und spaltschließend ausgebildet ist.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: German (DE)
Filing Language: German (DE)