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1. (WO2019007373) SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR FORMING A PROFILE OF A CAPACITOR THEREOF
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Pub. No.: WO/2019/007373 International Application No.: PCT/CN2018/094525
Publication Date: 10.01.2019 International Filing Date: 04.07.2018
IPC:
H01L 23/64 (2006.01) ,H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
64
Impedance arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
CHANGXIN MEMORY TECHNOLOGIES, INC. [CN/CN]; Room 630, Haiheng Building, No. 6, Cuiwei Road, Economic and Technological Development Zone, Hefei, Anhui 230000, CN
Inventors:
ZHU, Rongfu; CN
Agent:
METIS IP (CHENGDU) LLC; (No. 846 South Tianfu Road) Tianfu Innovation Center Chengdu, Sichuan 610213, CN
Priority Data:
201710539203.104.07.2017CN
Title (EN) SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR FORMING A PROFILE OF A CAPACITOR THEREOF
(FR) DISPOSITIF DE MÉMORISATION À SEMI-CONDUCTEURS ET PROCÉDÉ DE FORMATION D'UN PROFIL DE SON CONDENSATEUR
Abstract:
(EN) The present disclosure provide a method for forming a capacitor profile on a semiconductor. The method may include: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming an ion reflecting mask layer on the dielectric layer; forming a plurality of patterned openings by etching through the ion reflecting mask layer to expose the dielectric layer; and forming a plurality of trenching capacitor profiles by etching through the dielectric layer from the plurality of patterned openings, respectively, to expose the semiconductor substrate, wherein each trenching capacitor profile includes a bowing profile formed at 75%-95% of a height of the trenching capacitor profile above the semiconductor substrate.
(FR) La présente invention concerne un procédé de formation d'un profil de condensateur sur un semi-conducteur. Le procédé peut consister à : utiliser un substrat semi-conducteur ; former une couche diélectrique sur le substrat semi-conducteur ; former une couche de masque de réflexion d'ions sur la couche diélectrique ; former une pluralité d'ouvertures ayant fait l'objet d'une formation de motifs par gravure à travers la couche de masque de réflexion d'ions de façon à exposer la couche diélectrique ; et former une pluralité de profils de condensateur de tranchée par gravure à travers la couche diélectrique en partant respectivement de la pluralité d'ouvertures ayant fait l'objet d'une formation de motifs, pour exposer le substrat semi-conducteur, chaque profil de condensateur de tranchée comprenant un profil arqué formé à 75 % à 95 % d'une hauteur du profil de condensateur de tranchée au-dessus du substrat semi-conducteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)