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1. (WO2019006145) LEVEL SHIFTER FOR A WIDE LOW-VOLTAGE SUPPLY RANGE
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Pub. No.: WO/2019/006145 International Application No.: PCT/US2018/040056
Publication Date: 03.01.2019 International Filing Date: 28.06.2018
IPC:
H03K 19/088 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
08
using semiconductor devices
082
using bipolar transistors
088
Transistortransistor logic
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-ku, 160-8366, JP (JP)
Inventors:
GRAVES, Christopher, Michael; US
Agent:
DAVIS, Michael, A., Jr.; US
BASSUK, Lawrence, J.; US
Common
Representative:
TEXAS INSTRUMENTS INCORPORATED; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
Priority Data:
15/635,98028.06.2017US
Title (EN) LEVEL SHIFTER FOR A WIDE LOW-VOLTAGE SUPPLY RANGE
(FR) DISPOSITIF DE DÉCALAGE DE NIVEAU DESTINÉ À UNE LARGE PLAGE D'ALIMENTATION BASSE TENSION
Abstract:
(EN) A level shifter (400) is coupled to receive first and second input control signals (S1, S2) and to provide an output control signal (S3T). The level shifter (400) includes a level-shifting circuit (402) that has a first and a second PMOS transistor (MPL15, MPL16) and a first and a second NMOS transistor (MNL15, MNL16). A third NMOS transistor (MNL17) is coupled between an upper rail (VCCB) and the drain of the first PMOS transistor (MPL15), with the gate of the third NMOS transistor (MNL17) being controlled by the first input control signal (S1). A fourth NMOS transistor (MNL18) is coupled between the upper rail (VCCB) and the drain of the second PMOS transistor (MPL16), with the gate of the fourth NMOS transistor (MNL18) being controlled by the second input control signal (S2).
(FR) Selon la présente invention, un dispositif de décalage de niveau (400) est couplé de façon à recevoir des premier et second signaux de commande d'entrée (S1, S2) et à fournir un signal de commande de sortie (S3T). Le dispositif de décalage de niveau (400) comprend un circuit de décalage de niveau (402) qui possède un premier et un second transistor PMOS (MPL15, MPL16), ainsi qu'un premier et un deuxième transistor NMOS (MNL15, MNL16). Un troisième transistor NMOS (MNL17) est couplé entre un rail supérieur (VCCB) et le drain du premier transistor PMOS (MPL15), la grille du troisième transistor NMOS (MNL17) étant commandée par le premier signal de commande d'entrée (S1). Un quatrième transistor NMOS (MNL18) est couplé entre le rail supérieur (VCCB) et le drain du second transistor PMOS (MPL16), la grille du quatrième transistor NMOS (MNL18) étant commandée par le second signal de commande d'entrée (S2).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)