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1. (WO2019006135) CIRCUIT HAVING A PARALLEL VOLTAGE THRESHOLD ARCHITECTURE TO SUPPORT A WIDE VOLTAGE SUPPLY RANGE
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Pub. No.: WO/2019/006135 International Application No.: PCT/US2018/040040
Publication Date: 03.01.2019 International Filing Date: 28.06.2018
IPC:
H03K 17/687 (2006.01) ,H03K 19/0185 (2006.01) ,H03L 5/00 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
51
characterised by the use of specified components
56
by the use, as active elements, of semiconductor devices
687
the devices being field-effect transistors
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
0185
using field-effect transistors only
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
5
Automatic control of voltage, current, or power
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-ku, 160-8366, JP (JP)
Inventors:
GRAVES, Christopher, Michael; US
Agent:
DAVIS, Michael, A.; US
BASSUK, Lawrence, J.; US
Common
Representative:
TEXAS INSTRUMENTS INCORPORATED; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
Priority Data:
15/635,84428.06.2017US
Title (EN) CIRCUIT HAVING A PARALLEL VOLTAGE THRESHOLD ARCHITECTURE TO SUPPORT A WIDE VOLTAGE SUPPLY RANGE
(FR) CIRCUIT AYANT UNE ARCHITECTURE DE SEUIL DE TENSION PARALLÈLE POUR SUPPORTER UNE LARGE PLAGE D'ALIMENTATION EN TENSION
Abstract:
(EN) An output buffer (100) is coupled to receive an input voltage that can span a wide voltage supply range. The output buffer (100) includes a first metal oxide silicon (MOS) transistor (MPs1) having a first conductivity type and a first threshold voltage and a second MOS transistor (MpL1) having the first conductivity type and a second threshold voltage that is lower than the first threshold voltage. The first MOS transistor (MPS1) is coupled in parallel with the second MOS transistor (MPL1) between a first rail (VCCB) and a first signal line (VOUT)- The first MOS transistor (MPs1) and the second MOS transistor (MPL1) each receive a first signal (VP) on a respective gate.
(FR) La présente invention concerne un tampon de sortie (100) qui est couplé de sorte à recevoir une tension d'entrée qui peut s'étendre sur une large plage d'alimentation en tension. Le tampon de sortie (100) comprend un premier transistor métal-oxyde-silicium (MOS) (MPs1) ayant un premier type de conductivité et une première tension de seuil et un second transistor MOS (MpL1) ayant le premier type de conductivité et une seconde tension de seuil qui est inférieure à la première tension de seuil. Le premier transistor MOS (MPS1) est couplé en parallèle au second transistor MOS (MPL1) entre un premier rail (VCCB) et une première ligne de signal (VOUT). Le premier transistor MOS (MPs1) et le second transistor MOS (MPL1) reçoivent chacun un premier signal (VP) sur une grille respective.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)