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1. (WO2019006063) MULTI-LAYER CIRCUIT BOARD USING INTERPOSER LAYER AND CONDUCTIVE PASTE
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Pub. No.: WO/2019/006063 International Application No.: PCT/US2018/039906
Publication Date: 03.01.2019 International Filing Date: 28.06.2018
IPC:
H01L 21/02 (2006.01) ,H01L 21/48 (2006.01) ,H01L 23/14 (2006.01) ,H01L 51/00 (2006.01) ,H05K 1/09 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
09
Use of materials for the metallic pattern
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
SIERRA CIRCUITS, INC [US/US]; 1108 WEST EVELYN AVE. SUNNYVALE, California 94086, US
Inventors:
BAHL, Kenneth S.; US
KARAVAKIS, Konstantine; US
Agent:
CHESAVAGE, Jay; US
Priority Data:
15/635,20128.06.2017US
Title (EN) MULTI-LAYER CIRCUIT BOARD USING INTERPOSER LAYER AND CONDUCTIVE PASTE
(FR) CARTE DE CIRCUIT IMPRIMÉ MULTICOUCHE UTILISANT UNE COUCHE D'INTERPOSEUR ET UNE PÂTE CONDUCTRICE
Abstract:
(EN) A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
(FR) Une carte de circuit imprimé multicouche est formée en positionnant une sous-couche supérieure ayant des traces sur au moins un côté jusqu'à une ou plusieurs paires de couches composites, chaque couche composite comprenant une couche d'interposeur et une sous-couche. Chaque sous-couche qui est adjacente à une couche d'interposeur a une ouverture d'interconnexion, l'ouverture d'interconnexion étant positionnée adjacente à des interconnexions a un trou d'interconnexion plaqué ou une pastille sur chaque sous-couche correspondante. Chaque ouverture d'interposeur est remplie d'une pâte conductrice, et l'empilement de sous-couches supérieures et une ou plusieurs paires de couches composites sont placés dans une presse de stratification, l'enceinte étant évacuée, et une température élevée ainsi qu'une pression de stratification sont appliquées jusqu'à ce que la pâte conductrice ait fondu, connectant les interconnexions adjacentes, et les cartes sont stratifiées ensemble en une carte de circuit imprimé multicouche stratifiée achevée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)