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1. (WO2019005975) MEMORY TYPE WHICH IS CACHEABLE YET INACCESSIBLE BY SPECULATIVE INSTRUCTIONS
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Pub. No.: WO/2019/005975 International Application No.: PCT/US2018/039766
Publication Date: 03.01.2019 International Filing Date: 27.06.2018
IPC:
G06F 12/14 (2006.01) ,G06F 12/0802 (2016.01) ,G06F 12/0862 (2016.01) ,G06F 21/71 (2013.01) ,G06F 21/55 (2013.01) ,G06F 9/30 (2018.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
14
Protection against unauthorised use of memory
[IPC code unknown for G06F 12/0802][IPC code unknown for G06F 12/0862]
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70
Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71
to assure secure computing or processing of information
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50
Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
55
Detecting local intrusion or implementing counter-measures
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
Applicants:
NVIDIA CORPORATION [US/US]; 2701 San Tomas Expressway Santa Clara, CA 95050, US
Inventors:
BOGGS, Darrell; US
SEGELKEN, Ross; US
CORNABY, Mike; US
FORTINO, Nick; US
CHAUDHRY, Shailender; US
KHARTIKOV, Denis; US
MOOLEY, Alok; US
TUCK, Nathan; US
VREUGDENHIL, Gordon; US
Agent:
FARIS, Robert, W.; US
Priority Data:
62/526,23628.06.2017US
Title (EN) MEMORY TYPE WHICH IS CACHEABLE YET INACCESSIBLE BY SPECULATIVE INSTRUCTIONS
(FR) TYPE DE MÉMOIRE QUI PEUT ÊTRE ANTÉMÉMORISABLE TOUT EN ÉTANT INACCESSIBLE PAR DES INSTRUCTIONS SPÉCULATIVES
Abstract:
(EN) An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.
(FR) L'invention concerne un moyen architectural amélioré servant à adresser des attaques de mémoire cache de processeur sur la base d'une exécution spéculative définissant un nouveau type de mémoire qui est à la fois antémémorisable et inaccessible par spéculation. L'exécution spéculative ne peut pas accéder à ni exposer un emplacement de mémoire qui est inaccessible de manière spéculative. De tels mécanismes peuvent exclure certaines données sensibles en termes d'exposition par exécution spéculative. Des données qui doivent être protégées aux dépens de la performance peuvent être marquées de manière spécifique. Si le processeur est informé de l'emplacement de stockage de secrets dans la mémoire et s'il n'est pas autorisé à spéculer sur ces emplacements dans la mémoire, le processeur vérifiera que le processus qui tente d'accéder à ces emplacements dans la mémoire est privilégié à des fins d'accès à ces emplacements avant la lecture et la mise en cache de ces secrets. Une telle contre-mesure est efficace contre des attaques qui utilisent l'exécution spéculative pour divulguer des secrets en provenance d'une mémoire cache de processeur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)