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1. (WO2019005875) SERDES WITH ADAPTIVE CLOCK DATA RECOVERY
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Pub. No.: WO/2019/005875 International Application No.: PCT/US2018/039607
Publication Date: 03.01.2019 International Filing Date: 26.06.2018
IPC:
H03L 7/08 (2006.01) ,H03L 7/081 (2006.01) ,H04L 7/033 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
081
provided with an additional controlled phase shifter
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
033
using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
HAILU, Eskinder; US
PANDITA, Bupesh; US
BOYETTE, Jon; US
Agent:
HALLMAN, Jonathan W.; US
Priority Data:
16/017,30825.06.2018US
62/526,83129.06.2017US
Title (EN) SERDES WITH ADAPTIVE CLOCK DATA RECOVERY
(FR) SERDES À RÉCUPÉRATION DE DONNÉES D'HORLOGE ADAPTATIVE
Abstract:
(EN) A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value.
(FR) L'invention concerne un sérialiseur-désérialiseur (SerDes) à changement de vitesse qui utilise une première valeur de diviseur pour former une horloge divisée tout en désérialisant un flux de données en série avant une détection de verrouillage et qui utilise une seconde valeur de diviseur pour former la valeur d'horloge divisée après la détection de verrouillage, la seconde valeur de diviseur étant supérieure à la première valeur de diviseur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)