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1. (WO2019005468) MEMORY CELLS HAVING RESISTORS AND FORMATION OF THE SAME
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Pub. No.: WO/2019/005468 International Application No.: PCT/US2018/036985
Publication Date: 03.01.2019 International Filing Date: 12.06.2018
IPC:
H01L 45/00 (2006.01) ,H01L 25/065 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; Mail Stop 525 8000 South Federal Way P.O. Box 6 Boise, Idaho 83707-0006, US
Inventors:
PELLIZZER, Fabio; US
REDAELLI, Andrea; IT
PIROVANO, Agostino; IT
TORTORELLI, Innocenzo; IT
Agent:
KERN, Jacob T.; US
Priority Data:
15/632,53626.06.2017US
Title (EN) MEMORY CELLS HAVING RESISTORS AND FORMATION OF THE SAME
(FR) CELLULES DE MÉMOIRE AYANT DES RÉSISTANCES ET FORMATION DE CES DERNIÈRES
Abstract:
(EN) The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
(FR) La présente invention concerne des cellules de mémoire ayant des résistances et des procédés de formation de ces dernières. Un procédé donné à titre d'exemple consiste à former une première ligne conductrice, à former une seconde ligne conductrice et à former un élément de mémoire entre la première ligne conductrice et la seconde ligne conductrice. La formation de l'élément de mémoire peut consister à former un ou de plusieurs matériaux de mémoire et à former une résistance en série avec le ou les matériaux de mémoire. La résistance peut être configurée de sorte à réduire une décharge capacitive à travers l'élément de mémoire pendant une transition d'état de l'élément de mémoire.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)