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1. (WO2019005230) WORDLINE READ VOLTAGE OFFSETS IN SOLID STATE MEMORY DEVICES
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Pub. No.: WO/2019/005230 International Application No.: PCT/US2018/022502
Publication Date: 03.01.2019 International Filing Date: 14.03.2018
IPC:
G11C 11/56 (2006.01) ,G06N 3/02 (2006.01) ,G11C 16/26 (2006.01) ,G11C 29/02 (2006.01) ,G06F 3/06 (2006.01) ,G11C 16/04 (2006.01) ,G11C 29/50 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56
using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
26
Sensing or reading circuits; Data output circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
02
Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
04
using variable threshold transistors, e.g. FAMOS
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
04
Detection or location of defective memory elements
50
Marginal testing, e.g. race, voltage or current testing
Applicants:
WESTERN DIGITAL TECHNOLOGIES, INC. [US/US]; 5601 Great Oaks Parkway San Jose, CA 95119, US
Inventors:
KIRSHENBAUM, Roi; US
INBAR, Karin; US
GOLDENBERG, Idan; US
YANG, Nian, Niles; US
ROM, Rami; US
BAZARSKY, Alexander; US
NAVON, Ariel; US
REUSSWIG, Philip, David; US
Agent:
ALTMAN, Daniel, E.; US
Priority Data:
15/640,35630.06.2017US
Title (EN) WORDLINE READ VOLTAGE OFFSETS IN SOLID STATE MEMORY DEVICES
(FR) DÉCALAGES DE TENSION DE LECTURE DE LIGNE DE MOTS DANS DES DISPOSITIFS DE MÉMOIRE À SEMI-CONDUCTEURS
Abstract:
(EN) Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.
(FR) L'invention concerne des systèmes et des procédés permettant de générer un décalage de tension de lecture basé sur l'emplacement dans un dispositif de stockage de données. Des seuils optimaux de tension de lecture varient à travers les éléments de mémoire d'un dispositif. Cependant, les dispositifs de stockage de données sont souvent limités dans le nombre de seuils de tension de lecture qui peuvent être conservés dans le dispositif. Ainsi, il n'est pas possible de maintenir des paramètres de tension de lecture optimaux pour chaque élément de mémoire à l'intérieur d'un dispositif. Les systèmes et les procédés décrits ici fournissent une précision accrue de seuils de tension de lecture lorsqu'ils sont appliqués à des éléments de mémoire à l'intérieur d'un emplacement spécifique dans un dispositif, en permettant l'utilisation de décalages de tension de lecture basés sur l'emplacement, en fonction d'un emplacement relatif de l'élément de mémoire en cours de lecture à partir de. Les décalages de tension de lecture peuvent être déterminés sur la base de l'application d'un réseau neuronal à des données concernant des seuils de tension de lecture optimaux déterminés à partir d'au moins un échantillon d'éléments de mémoire dans un dispositif.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)