Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019005221) THREE-DIMENSIONAL MEMORY DEVICE HAVING DIRECT SOURCE CONTACT AND METAL OXIDE BLOCKING DIELECTRIC AND METHOD OF MAKING THEREOF
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/005221 International Application No.: PCT/US2018/020126
Publication Date: 03.01.2019 International Filing Date: 28.02.2018
IPC:
H01L 27/1157 (2017.01) ,H01L 27/11582 (2017.01) ,H01L 21/311 (2006.01)
[IPC code unknown for H01L 27/1157][IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
Applicants:
SANDISK TECHNOLOGIES LLC [US/US]; 6900 North Dallas Parkway Suite 325 Plano, Texas 75024, US
Inventors:
MAKALA, Raghuveer S.; US
KANAKAMEDALA, Senaka Krishna; US
ZHANG, Yanli; US
LEE, Yao-Sheng; US
Agent:
RADOMSKY, Leon; US
COHN, Joanna; US
CONNOR, David; US
GAYOSO, Tony; US
GEMMELL, Elizabeth; US
GILL, Matthew; US
GREGORY, Shaun; US
GUNNELS, Zarema; US
HANSEN, Robert; US
HUANG, Stephen; US
HYAMS, David; US
JOHNSON, Timothy; US
MAZAHERY, Benjamin; US
MURPHY, Timothy; US
NGUYEN, Jacqueline; US
O'BRIEN, Michelle; US
PARK, Byeongju; US
RUTT, Steven; US
SIMON, Phyllis; US
SMITH, Jackson R.; US
SULSKY, Martin; US
Priority Data:
15/633,13126.06.2017US
Title (EN) THREE-DIMENSIONAL MEMORY DEVICE HAVING DIRECT SOURCE CONTACT AND METAL OXIDE BLOCKING DIELECTRIC AND METHOD OF MAKING THEREOF
(FR) DISPOSITIF DE MÉMOIRE TRIDIMENSIONNEL AYANT UN CONTACT DE SOURCE DIRECTE ET UN DIÉLECTRIQUE DE BLOCAGE D'OXYDE MÉTALLIQUE ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.
(FR) L'invention concerne une couche sacrificielle à niveau sangle et un empilement alterné de couches isolantes et de couches de matériau d'espacement qui sont formées sur un substrat. Un réseau de structures d'empilement de mémoire est formé à travers l'empilement alterné et la couche sacrificielle à niveau sangle. Chaque film de mémoire dans les structures d'empilement de mémoire comprend un diélectrique de blocage d'oxyde métallique. Après la formation d'une cavité source par retrait de la couche sacrificielle de niveau sangle, un procédé de gravure de couche atomique peut être utilisé pour retirer des parties des diélectriques de blocage d'oxyde métallique au niveau de la cavité source. Des parois latérales externes de canaux semi-conducteurs dans les structures d'empilement de mémoire sont exposées par des processus de gravure supplémentaires, et une couche de sangle source est sélectivement déposée dans la cavité source en contact avec le canal semi-conducteur. Si les couches de matériau d'espacement sont des couches de matériau sacrificiel, tous les volumes des couches de matériau sacrificiel peuvent être remplacés par les couches électroconductrices.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)