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1. (WO2019005167) DUAL BOTTOM ELECTRODE FOR MEMORY APPLICATIONS AND METHODS TO FORM THE SAME
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Pub. No.: WO/2019/005167 International Application No.: PCT/US2017/040510
Publication Date: 03.01.2019 International Filing Date: 30.06.2017
IPC:
H01L 45/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
STRUTT, Nathan [US/US]; US
WU, Stephen Y. [US/US]; US
ASURI, Namrata S. [IN/US]; US
GLASSMAN, Timothy E. [US/US]; US
GOLONZKA, Oleg [US/US]; US
MUKHERJEE, Niloy [IN/US]; US
SEGHETE, Dragos [US/US]; US
WIEGAND, Christopher J. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
STRUTT, Nathan; US
WU, Stephen Y.; US
ASURI, Namrata S.; US
GLASSMAN, Timothy E.; US
GOLONZKA, Oleg; US
MUKHERJEE, Niloy; US
SEGHETE, Dragos; US
WIEGAND, Christopher J.; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) DUAL BOTTOM ELECTRODE FOR MEMORY APPLICATIONS AND METHODS TO FORM THE SAME
(FR) ÉLECTRODE INFÉRIEURE DOUBLE POUR APPLICATIONS DE MÉMOIRE ET PROCÉDÉS POUR FORMER CELLE-CI
Abstract:
(EN) An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a substrate. The dual bottom electrode includes a first conductive layer disposed above a substrate, a second conductive layer disposed above the first conductive layer and an intermediate layer between the first conductive layer and the second conductive layer, where the intermediate layer includes oxygen. A switching layer is disposed on the dual bottom electrode layer. An oxygen exchange layer is disposed on the switching layer and a top electrode is disposed on the switching layer.
(FR) L'invention se rapporte à une approche visant à intégrer un dispositif de mémoire vive résistive (RRAM) sur une couche d'électrode inférieure double. Dans un exemple, un dispositif de mémoire vive résistive (RRAM) comprend une électrode inférieure double disposée au-dessus d'un substrat. L'électrode inférieure double comprend une première couche conductrice disposée au-dessus d'un substrat, une deuxième couche conductrice disposée au-dessus de la première couche conductrice et une couche intermédiaire entre la première couche conductrice et la deuxième couche conductrice, la couche intermédiaire comprenant de l'oxygène. Une couche de commutation est disposée sur la couche d'électrode inférieure double. Une couche d'échange d'oxygène est disposée sur la couche de commutation et une électrode supérieure est formée sur la couche d'échange d'oxygène.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)