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1. (WO2019005152) DIE BACK SIDE STRUCTURES FOR WARPAGE CONTROL
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Pub. No.: WO/2019/005152 International Application No.: PCT/US2017/040482
Publication Date: 03.01.2019 International Filing Date: 30.06.2017
IPC:
H01L 23/485 (2006.01) ,H01L 23/36 (2006.01) ,H01L 23/00 (2006.01) ,H01L 21/027 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, California 95054, US
Inventors:
EID, Feras; US
GUTHIKONDA, Venkata Suresh R.; US
DEVASENATHIPATHY, Shankar; US
JHA, Chandra M.; US
CHANG, Je-Young; US
YAZZIE, Kyle; US
RAGHAVAN, Prasanna; US
MALATKAR, Pramod; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) DIE BACK SIDE STRUCTURES FOR WARPAGE CONTROL
(FR) STRUCTURES DE FACE ARRIÈRE DE PUCE POUR UNE COMMANDE DE GAUCHISSEMENT
Abstract:
(EN) A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.
(FR) La présente invention porte sur une couche de base ayant un raidisseur et sur des procédés de formation d'un raidisseur. Une ou plusieurs puces sont formées sur la couche de base. Chaque puce comporte une surface de face avant qui est couplée électriquement à la couche de base et une surface de face arrière qui est opposée à la surface de face avant. Une couche de raidissement (ou un raidisseur) est formée sur la surface de face arrière d'au moins l'une des puces. La couche de raidissement peut être directement couplée à la surface de face arrière de la ou des puces sans couche adhésive. La couche de raidissement peut comprendre un ou plusieurs matériaux, comprenant un métal et/ou un alliage métallique et/ou une céramique. La couche de raidissement peut être formée de sorte à réduire le gauchissement sur la base de la couche de base et des puces. Le ou les matériaux de la couche de raidissement peuvent être formés à l'aide d'un spray froid.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)