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1. (WO2019005129) SPIN HALL EFFECT MAGNETIC RANDOM-ACCESS MEMORY BITCELL
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CLAIMS

What is claimed is:

1. A semiconductor device including a spin Hall effect (SHE) magnetore si stive random-access memory (MRAM) bitcell, the device comprising:

first and second access transistors in a device level of the semiconductor device;

a wordline in the device level and coupled to gate terminals of the first and second access transistors;

a first source line and a second source line in a lowest metal interconnect layer of the semiconductor device and coupled to source terminals of the first and second access transistors, respectively;

spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device and coupling drain terminals of the first and second access transistors;

a magnetic tunnel junction (MTJ) in an upper portion of the second lowest metal interconnect layer and having a bottom terminal coupled to the spin Hall metal; and

a bitline in a third lowest metal interconnect layer of the semiconductor device and coupled to a top terminal of the MTJ.

2. The device of claim 1, wherein the bitcell comprises only two transistors and one MTJ.

3. The device of claim 1, wherein each of the first and second access transistors comprises two gate electrodes for coupling two corresponding source regions to a single drain region.

4. The device of claim 3, wherein the wordline comprises two corresponding wordlines respectively coupled to the two gate electrodes of each of the first and second access transistors.

5. The device of claim 3, wherein each of the first and second access transistors further comprises:

two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines; and

a drain contact coupling the drain region to the drain terminal of a respective one of the first and second access transistors.

6. The device of claim 1, further comprising first and second metal stubs in a lowest portion of the second lowest metal interconnect layer, the first and second metal stubs respectively coupling the drain terminals of the first and second access transistors to the spin Hall metal.

7. The device of claim 6, wherein the MTJ is equidistant to the first and second metal stubs.

8. The device of claim 1 , wherein the MTJ comprises:

a free magnet coupled to the spin Hall metal;

a fixed magnet coupled to the bitline; and

a tunnel barrier separating the free magnet and the fixed magnet.

9. The device of claim 1 , wherein the MTJ overlaps one of the first and second source lines in a vertical direction.

10. The device of claim 1, wherein the spin Hall metal comprises one or more of beta tantalum (β-Ta), beta tungsten (β-W), and platinum (Pt).

1 1. The device of any of claims 1-10, wherein the semiconductor device is a microprocessor and the bitcell is an embedded memory cell of the microprocessor.

12. A spin Hall effect (SHE) magnetoresi stive random-access memory (MRAM) comprising:

a SHE-MRAM bitcell array including

wordlines extending in a first direction,

first source lines and second source lines extending in a second direction crossing the first direction,

bitlines extending in the second direction, and

bitcell s where the wordlines cross the first source lines, the second source lines, and the bitlines, each bitcell including

first and second access transistors having gate terminals coupled to one of the wordlines and source terminals coupled to respective ones of the first and second source lines,

spin Hall metal coupling drain terminals of the first and second access transistors, and

a magnetic tunnel junction (MTJ) having a bottom terminal coupled to the spin Hall metal and a top terminal coupled to one of the bitlines; and

a write driver to write data of a first state to one of the bitcells by

driving the one of the wordlines for a first period to turn on the first and second access transistors while supplying voltage of a first polarity to the first source line and supplying voltage of a second polarity opposite the first polarity to the second source line,

driving the one of the wordlines for a second period following the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line, and supplying a first voltage to the one of the bitlines for a third period overlapping and following the second period and while not driving the one of the wordlines during the following portion of the third period.

13. The SHE-MRAM of claim 12, further comprising a customizing circuit to adjust a level of the first voltage and a length of the overlapping portion of the third period.

14. The SHE-MRAM of claim 13, wherein the customizing circuit is further to adjust lengths of the first and second periods.

15. The SHE-MRAM of claim 12, wherein the write driver is further to write data of a second state opposite the first state to the one of the bitcells by:

driving the one of the wordlines for the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line;

driving the one of the wordlines for the second period while supplying the first polarity voltage to the first source line and supplying the second polarity voltage to the second source line; and

supplying the first voltage to the one of the bitlines for the third period while not driving the one of the wordlines during the following portion of the third period.

16. The SHE-MRAM of any of claims 12-15, further comprising a read driver to read data from the one of the bitcells by driving the one of the wordlines while supplying the second polarity voltage to the first and second source lines and while supplying a second voltage to the one of the bitlines.

17. The SHE-MRAM of claim 16, further comprising a customizing circuit to adjust a level of the second voltage.

18. The SHE-MRAM of any of claim 16, wherein the second voltage is different than the first voltage.

19. A method of writing data to a spin Hall effect (SHE) magnetoresi stive random-access memory (MRAM) comprising a SHE-MRAM bitcell array including wordlines extending in a first direction, first source lines and second source lines extending in a second direction crossing the first direction, bitlines extending in the second direction, and bitcells where the wordlines cross the first source lines, the second source lines, and the bitlines, each bitcell including first and second access transistors having gate terminals coupled to one of the wordlines and source terminals coupled to respective ones of the first and second source lines, spin Hall metal coupling drain terminals of the first and second access transistors, and a magnetic tunnel junction (MTJ) having a bottom terminal coupled to the spin Hall metal and a top terminal coupled to one of the bitlines, the method comprising:

writing data of a first state to one of the bitcells by

driving the one of the wordlines for a first period to turn on the first and second access transistors while supplying voltage of a first polarity to the first source line and supplying voltage of a second polarity opposite the first polarity to the second source line,

driving the one of the wordlines for a second period following the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line, and supplying a first voltage to the one of the bitlines for a third period overlapping and following the second period and while not driving the one of the wordlines during the following portion of the third period.

20. The method of claim 19, wherein the SHE-MRAM further comprises a customizing circuit, the method further comprising adjusting a level of the first voltage and a length of the overlapping portion of the third period using the customizing circuit.

21. The method of any of claims 19-20, further comprising writing data of a second state opposite the first state to the one of the bitcells by:

driving the one of the wordlines for the first period while supplying the second polarity voltage to the first source line and supplying the first polarity voltage to the second source line;

driving the one of the wordlines for the second period while supplying the first polarity voltage to the first source line and supplying the second polarity voltage to the second source line; and

supplying the first voltage to the one of the bitlines for the third period while not driving the one of the wordlines during the following portion of the third period.

22. A method of manufacturing a spin Hall effect (SHE) magnetoresi stive random-access memory (MRAM) bitcell array comprising bitcells where wordlines cross first source lines, second source lines, and bitlines, the method comprising:

forming the wordlines on a substrate in a device level of a semiconductor device, the wordlines extending in a first direction;

for each bitcell, forming first and second access transistors in the device level, the first and second access transistors having gate terminals coupled to one of the wordlines;

forming the first source lines and the second source lines in a lowest metal interconnect layer of the semiconductor device, the first and second source lines extending in a second direction crossing the first direction, each first access transistor being coupled to one of the first source lines and each second access transistor being coupled to one of the second source lines;

for each bitcell, forming spin Hall metal in a lower portion of a second lowest metal interconnect layer of the semiconductor device, the spin Hall metal coupling drain terminals of the first and second access transistors;

for each bitcell, forming a magnetic tunnel junction (MTJ) in an upper portion of the second lowest metal interconnect layer, the MTJ having a bottom terminal coupled to the spin Hall metal; and

forming the bitlines in a third lowest metal interconnect layer of the semiconductor device, the bitlines extending in the second direction, each MTJ having a top terminal coupled to one of the bitlines.

23. The method of claim 22, wherein for each bitcell, the forming of each of the first and second access transistors comprises forming two gate electrodes for coupling two corresponding source regions to a single drain region.

24. The method of claim 23, wherein for each bitcell, the forming of each of the first and second access transistors further comprises:

forming two corresponding source contacts coupling the two corresponding source regions to a respective one of the first and second source lines; and forming a drain contact coupling the drain region to the drain terminal of a respective one of the first and second access transistors.

25. The method of claim 24, wherein the forming of each of the first and second access transistors of adjacent ones of the bitcells in the second direction comprises forming a shared said source region and a shared said corresponding source contact.