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1. (WO2019005111) DIVERSE TRANSISTOR CHANNEL MATERIALS ENABLED BY THIN, INVERSE-GRADED, GERMANIUM-BASED LAYER
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Pub. No.: WO/2019/005111 International Application No.: PCT/US2017/040317
Publication Date: 03.01.2019 International Filing Date: 30.06.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/66 (2006.01) ,H01L 21/8238 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
JAMBUNATHAN, Karthik; US
BOMBERGER, Cory C.; US
GLASS, Glenn A.; US
MURTHY, Anand S.; US
NAM, Ju H.; US
GHANI, Tahir; US
Agent:
BRODSKY, Stephen I.; US
Priority Data:
Title (EN) DIVERSE TRANSISTOR CHANNEL MATERIALS ENABLED BY THIN, INVERSE-GRADED, GERMANIUM-BASED LAYER
(FR) DIVERS MATÉRIAUX DE CANAL DE TRANSISTOR ACTIVÉS PAR UNE COUCHE MINCE À BASE DE GERMANIUM À GRADIENT INVERSE
Abstract:
(EN) Techniques are disclosed for forming diverse transistor channel materials enabled by a thin, inverse-graded, germanium (Ge)-based layer. The thin, inverse-graded, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the inverse grading of the Ge concentration in the layer, where the Ge concentration is relatively greatest near the substrate and relatively lowest near the overlying channel material layer. In addition to the inverse-graded Ge concentration, the Ge-based layer may be characterized by the nucleation, and predominant containment, of defects at/near the interface between the substrate and the Ge-based layer.
(FR) L'invention concerne des techniques pour former divers matériaux de canal de transistor activés par une couche mince à base de germanium (Ge) à gradient inverse. La couche mince à base de Ge à gradient inverse (par exemple, ayant une épaisseur maximale de 500 nm) peut ensuite servir de gabarit pour la croissance d'un matériau de canal PMOS contraint en compression et d'un matériau de canal NMOS contraint en traction afin d'obtenir des gains de mobilité respectivement des trous et des électrons dans les régions de canal des dispositifs. Une telle couche à base de Ge relativement mince peut être formée avec des niveaux de qualité/relaxation de surface appropriés du fait de la gradation inverse de la concentration de Ge dans la couche, la concentration de Ge étant relativement la plus élevée à proximité du substrat et relativement la plus faible à proximité de la couche de matériau de canal surjacente. En plus de la concentration de Ge à gradient inverse, la couche à base de Ge peut être caractérisée par la nucléation et le confinement prédominant des défauts au niveau/à proximité de l'interface entre le substrat et la couche à base de Ge.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)