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1. (WO2019005068) MULTIPLE RETICLE FIELD SEMICONDUCTOR DEVICES
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Pub. No.: WO/2019/005068 International Application No.: PCT/US2017/039990
Publication Date: 03.01.2019 International Filing Date: 29.06.2017
IPC:
H01L 21/768 (2006.01) ,H01L 21/027 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
BURTON, Edward A.; US
BOHR, Mark T.; US
KELLEY, Murray Fitzpatrick; US
KLAUSER, Shawn Michael; US
Agent:
MALONEY, Neil F.; US
Priority Data:
Title (EN) MULTIPLE RETICLE FIELD SEMICONDUCTOR DEVICES
(FR) DISPOSITIFS À SEMI-CONDUCTEUR À MULTIPLES ZONES RÉTICULAIRES
Abstract:
(EN) Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.
(FR) L'invention concerne des techniques de fabrication de dispositifs de circuit intégré qui couvrent de multiples zones réticulaires. Des circuits intégrés formés à l'intérieur de zones réticulaires séparées sont mis en contact électrique l'un avec l'autre par chevauchement de zones réticulaires pour former une interconnexion conductrice se chevauchant. Cette interconnexion conductrice se chevauchant connecte électriquement une couche d'interconnexion d'une première zone réticulaire avec une couche d'interconnexion d'une seconde zone réticulaire latéralement adjacente. L'interconnexion conductrice se chevauchant s'étend dans une zone de découpe commune entre des zones réticulaires adjacentes.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)