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1. (WO2019005057) NON-VOLATILE LOGIC CIRCUIT EMPLOYING LOW-POWER MOSFET ENABLED BY NON-VOLATILE LATCHED OUTPUTS
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Pub. No.: WO/2019/005057 International Application No.: PCT/US2017/039899
Publication Date: 03.01.2019 International Filing Date: 29.06.2017
IPC:
H01L 27/11521 (2017.01) ,H01L 21/8238 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/66 (2006.01)
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
AVCI, Uygar E.; US
MORRIS, Daniel H.; US
YOUNG, Ian A.; US
Agent:
BRODSKY, Stephen I.; US
Priority Data:
Title (EN) NON-VOLATILE LOGIC CIRCUIT EMPLOYING LOW-POWER MOSFET ENABLED BY NON-VOLATILE LATCHED OUTPUTS
(FR) CIRCUIT LOGIQUE NON VOLATILE UTILISANT UN MOSFET DE FAIBLE PUISSANCE ACTIVÉ PAR DES SORTIES VERROUILLÉES NON VOLATILES
Abstract:
(EN) Techniques are disclosed for forming a non-volatile hybrid logic circuit employing low-power MOSFET enabled by non-volatile latched outputs. The hybrid arrangement is able to achieve both circuit-level non-volatility and relatively lower power levels, neither of which can be attained using MOSFET/CMOS or non-volatile logic/memory elements on their own. Further, standard MOSFET/CMOS alone cannot be used with relatively low threshold voltages (VTs) due to leakage currents and lack of non-volatility during power gating, for example. Accordingly, the non-volatile elements of the hybrid circuit serve as flip-flops or register files to provide non-volatile latched outputs for preserving the state of the logic circuit even when not receiving power. Thus, in the hybrid circuit arrangement, low-VDD, low-VT MOSFET devices are operatively coupled with non-volatile logic/memory elements (e.g., spintronic devices, ferroelectric devices, magnetoresistive devices) to enable energy efficient, low-VDD, low-VT, non-volatile operation for a logic circuit.
(FR) L'invention concerne des techniques servant à former un circuit logique hybride non volatile utilisant un MOSFET de faible puissance activé par des sorties verrouillées non volatiles. L'agencement hybride est capable d'obtenir à la fois une non-volatilité au niveau circuit et des niveaux de puissance relativement inférieurs, aucun ne pouvant être obtenu à l'aide de MOSFET/CMOS ou d'éléments de mémoire/logique non volatils seuls. En outre, le MOSFET/CMOS standard seul ne peut pas être utilisé avec des tensions de seuil relativement faibles (VT) en raison de courants de fuite et d'un manque de non-volatilité pendant une coupure de puissance, par exemple. En conséquence, les éléments non volatils du circuit hybride servent de bascules bistables ou de fichiers de registre pour fournir des sorties verrouillées non volatiles pour préserver l'état du circuit logique même en cas de coupure d'énergie. Ainsi, dans l'agencement de circuit hybride, des dispositifs MOSFET à faible tension VDD et basse tension sont couplés fonctionnellement à des éléments de mémoire/logique non volatils (par exemple, des dispositifs spintroniques, des dispositifs ferroélectriques, des dispositifs magnétorésistifs) pour permettre un fonctionnement à faible consommation d'énergie, à faible tension VDD, à basse tension et non volatile pour un circuit logique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)