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1. (WO2019004991) QUANTUM COMPUTING ASSEMBLIES
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Pub. No.: WO/2019/004991 International Application No.: PCT/US2017/039167
Publication Date: 03.01.2019 International Filing Date: 25.06.2017
IPC:
H01L 25/065 (2006.01) ,H01L 23/538 (2006.01) ,H01L 23/58 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
Inventors:
ELSHERBINI, Adel A.; US
CLARKE, James S.; US
SWAN, Johanna M.; US
LIFF, Shawna M.; US
FALCON, Javier A.; US
NAM, Ye Seul; US
ROBERTS, Jeanette M.; US
CAUDILLO, Roman; US
Agent:
ZAGER, Laura A.; US
Priority Data:
Title (EN) QUANTUM COMPUTING ASSEMBLIES
(FR) ASSEMBLAGES DE CALCULATEURS QUANTIQUES
Abstract:
(EN) Disclosed herein are quantum computing (QC) assemblies, as well as related methods and devices. In some embodiments, a QC assembly may include a package substrate having a first face and an opposing second face, a quantum processing die coupled to the first face of the package substrate, and a control die coupled to the second face of the package substrate. The package substrate may include conductive structures electrically coupling the quantum processing die to the control die.
(FR) La présente invention concerne des assemblages de calculateurs quantiques (QC), ainsi que des dispositifs et des procédés associés. Dans certains modes de réalisation, un assemblage QC peut comprendre un substrat de boîtier ayant une première face et une seconde face opposée, une puce de traitement quantique couplée à la première face du substrat de boîtier, et une puce de commande couplée à la seconde face du substrat de boîtier. Le substrat de boîtier peut comprendre des structures conductrices couplant électriquement la puce de traitement quantique à la puce de commande.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)