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1. (WO2019003840) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Pub. No.: WO/2019/003840 International Application No.: PCT/JP2018/021733
Publication Date: 03.01.2019 International Filing Date: 06.06.2018
IPC:
H01L 21/82 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
株式会社ソシオネクスト SOCIONEXT INC. [JP/JP]; 神奈川県横浜市港北区新横浜二丁目10番23 2-10-23 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa 2220033, JP
Inventors:
岩堀 淳司 IWAHORI Junji; JP
Agent:
特許業務法人前田特許事務所 MAEDA & PARTNERS; 大阪府大阪市北区堂島浜1丁目2番1号 新ダイビル23階 Shin-Daibiru Bldg. 23F, 2-1, Dojimahama 1-chome, Kita-ku, Osaka-shi, Osaka 5300004, JP
Priority Data:
2017-12507727.06.2017JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR
(JA) 半導体集積回路装置
Abstract:
(EN) This semiconductor integrated circuit device that uses a nanowire FET has a circuit block in which a plurality of cell rows (CR1-CR3) comprising a plurality of standard cells (C) aligned in an X-direction are aligned side by side in a Y-direction. The plurality of standard cells (C) are each provided with a plurality of nanowires (NW) extending in the X-direction and disposed at a predetermined pitch (Pn) in the Y-direction. In the plurality of standard cells (C), the cell height (Hc), which is the size in the Y-direction, is M times (where M is an odd number) of half the pitch (Pn) of the nanowires (NW).
(FR) L'invention concerne un dispositif de circuit intégré à semi-conducteur qui utilise un transistor FET à nanofils comprenant un bloc de circuit dans lequel une pluralité de rangées de cellules (CR1-CR3) comprenant une pluralité de cellules standards (C) alignées dans une direction X sont alignées côte à côte dans une direction Y. La pluralité de cellules standards (C) comprennent chacune une pluralité de nanofils (NW) s'étendant dans la direction X et disposés à un pas prédéterminé (Pn) dans la direction Y. Dans la pluralité de cellules standards (C), la hauteur de cellule (Hc), qui est la taille dans la direction Y, est M fois (où M est un nombre impair) la moitié du pas (Pn) des nanofils (NW).
(JA) ナノワイヤFETを用いた半導体集積回路装置は、回路ブロックにおいて、X方向に並ぶ複数のスタンダードセル(C)からなるセル列(CR1~CR3)が、Y方向において複数、並べて配置されている。複数のスタンダードセル(C)は、X方向に延び、Y方向において所定ピッチ(Pn)で配置された複数のナノワイヤ(NW)を備える。複数のスタンダードセル(C)は、Y方向におけるサイズであるセル高さ(Hc)が、ナノワイヤ(NW)のピッチ(Pn)の半分のM倍(Mは奇数)である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)