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1. (WO2019003047) SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/003047 International Application No.: PCT/IB2018/054487
Publication Date: 03.01.2019 International Filing Date: 19.06.2018
IPC:
H01L 29/786 (2006.01) ,G11C 11/405 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 21/8242 (2006.01) ,H01L 27/06 (2006.01) ,H01L 27/088 (2006.01) ,H01L 27/108 (2006.01) ,H01L 27/1156 (2017.01) ,H01L 29/788 (2006.01) ,H01L 29/792 (2006.01) ,H03K 19/177 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403
with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
405
with three charge-transfer gates, e.g. MOS transistors, per cell
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8242
Dynamic random access memory structures (DRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
[IPC code unknown for H01L 27/1156]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
792
with charge trapping gate insulator, e.g. MNOS-memory transistor
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
173
using elementary logic circuits as components
177
arranged in matrix form
Applicants:
株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 神奈川県厚木市長谷398 398, Hase, Atsugi-shi, Kanagawa 2430036, JP
Inventors:
山崎舜平 YAMAZAKI, Shunpei; JP
松林大介 MATSUBAYASHI, Daisuke; JP
大貫達也 ONUKI, Tatsuya; JP
Priority Data:
2017-12557827.06.2017JP
2017-12560827.06.2017JP
2018-03299227.02.2018JP
Title (EN) SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置、および半導体装置の作製方法
Abstract:
(EN) Provided is a semiconductor device enabling high integration. Specifically provided is a semiconductor device which has a transistor, an interlayer film, and a first conductor, and in which: the transistor is provided with an oxide upon a first insulator, a second conductor upon the oxide, a second insulator provided between the oxide and the second conductor and provided in a manner touching the side surfaces of the second conductor, and a third insulator provided to the side surfaces of the second conductor, with the second insulator sandwiched therebetween; the oxide has a first region, a second region, and a third region; the first region overlaps with the second conductor; the second region is provided between the first region and the third region; the third region has a lower resistance than the second region; the second region has a lower resistance than the first region; the interlayer film is provided upon the first insulator and upon the oxide; the first conductor is electrically connected to the third region; the third region overlaps with any one among the third insulator, the first conductor, and the interlayer film; and the top surface of the third insulator is aligned with the top surface of the interlayer film.
(FR) L'invention concerne un dispositif à semi-conducteur permettant une haute intégration. Plus précisément, l'invention concerne un dispositif à semi-conducteur qui comporte un transistor, un film intermédiaire et un premier conducteur, et dans lequel : le transistor comprend un oxyde sur un premier isolant, un second conducteur sur l'oxyde, un second isolant disposé entre l'oxyde et le second conducteur et disposé de manière à toucher les surfaces latérales du second conducteur, et un troisième isolant disposé sur les surfaces latérales du second conducteur, le second isolant étant pris en sandwich entre ceux-ci; l'oxyde a une première région, une seconde région et une troisième région; la première région chevauche le second conducteur; la seconde région est disposée entre la première région et la troisième région; la troisième région a une résistance inférieure à la seconde région; la seconde région a une résistance inférieure à celle de la première région; le film intermédiaire est disposé sur le premier isolant et sur l'oxyde; le premier conducteur est électroconnecté à la troisième région; la troisième région chevauche l'un quelconque parmi le troisième isolant, le premier conducteur, et le film intermédiaire; et la surface supérieure du troisième isolant est alignée avec la surface supérieure du film intermédiaire.
(JA) 高集積化が可能な半導体装置を提供する。 トランジスタ、 層間膜および第1の導電体を有し、 トランジスタは第1の絶縁体上の酸化物と、 酸化 物上の第2の導電体と、 酸化物と第2の導電体の間に設けられ、 かつ第2の導電体の側面と接するよ うに設けられた第2の絶縁体と、 第2の絶縁体を間に挟み、 第2の導電体の側面に設けられた、 第3 の絶縁体を有し、酸化物は第1の領域、第2の領域、第3の領域を有し、第1の領域は、第2の導電 体と重なり、第2の領域は、第1の領域と、第3の領域と、の間に設けられ、第3の領域は、第2の 領域よりも低抵抗であり、 第2の領域は、 第1の領域よりも低抵抗であり、 層間膜は、 第1の絶縁体 上、 および酸化物上に設けられ、 第1の導電体は第3の領域と電気的に接続され、 第3の領域は第3 の絶縁体、 第1の導電体、 および層間膜のいずれか一と重なり、 第3の絶縁体の上面は層間膜の上面 と一致する半導体装置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)