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1. (WO2019002541) SUBSTRATE FOR ELECTRICAL CIRCUITS AND METHOD FOR PRODUCING SUCH A SUBSTRATE
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Pub. No.: WO/2019/002541 International Application No.: PCT/EP2018/067558
Publication Date: 03.01.2019 International Filing Date: 29.06.2018
IPC:
H05K 1/05 (2006.01) ,H01L 23/373 (2006.01) ,B32B 9/06 (2006.01) ,H01L 23/08 (2006.01) ,H01L 23/10 (2006.01) ,H05K 1/02 (2006.01) ,B32B 15/12 (2006.01) ,B32B 15/20 (2006.01) ,B32B 29/08 (2006.01) ,H05K 1/03 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
03
Use of materials for the substrate
05
Insulated metal substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373
Cooling facilitated by selection of materials for the device
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
9
Layered products essentially comprising a particular substance not covered by groups B32B11/-B32B29/137
04
comprising such substance as the main or only constituent of a layer, next to another layer of a specific substance
06
of paper or cardboard
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
06
characterised by the material of the container or its electrical properties
08
the material being an electrical insulator, e.g. glass
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
10
characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
15
Layered products essentially comprising metal
04
comprising metal as the main or only constituent of a layer, next to another layer of a specific substance
12
of paper or cardboard
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
15
Layered products essentially comprising metal
20
comprising aluminium or copper
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
29
Layered products essentially comprising paper or cardboard
08
Corrugated paper, corrugated cardboard
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
03
Use of materials for the substrate
Applicants:
ROGERS GERMANY GMBH [DE/DE]; Am Stadtwald 2 92676 Eschenbach, DE
Inventors:
SCHMIDT, Karsten; DE
WILLIAMS, Shawn; US
TRAVITZKY, Nahum; DE
GREIL, Peter; DE
BONET, Alexander; DE
Agent:
MÜLLER, F. Peter; DE
Priority Data:
10 2017 114 442.029.06.2017DE
Title (EN) SUBSTRATE FOR ELECTRICAL CIRCUITS AND METHOD FOR PRODUCING SUCH A SUBSTRATE
(FR) SUBSTRAT POUR CIRCUITS ÉLECTRIQUES ET PROCÉDÉ DE FABRICATION D'UN TEL SUBSTRAT
(DE) SUBSTRAT FÜR ELEKTRISCHE SCHALTKREISE UND VERFAHREN ZUR HERSTELLUNG EINES DERARTIGEN SUBSTRATES
Abstract:
(EN) The invention relates to a substrate (1) for electrical circuits, comprising at least one paper ceramic layer (2) having a top side and bottom side (2a, 2b), which has a pore structure consisting of a plurality of pore-shaped cavities, characterized in that the pore-shaped cavities of the pore structure, at least in the region of the top and/or bottom side (2a, 2b) of the paper ceramic layer (2), are filled, using an infiltration method, with a metal or a metal alloy such that at least one metallization layer (3, 4) having a layer thickness (d2, d3) between 0.1 to 10 μιτι forms on the top and/or bottom side (2a, 2b). The invention further relates to a method for producing such a substrate, and modules derived therefrom, in particular power modules.
(FR) L’invention concerne un substrat (1) pour circuits électriques comprenant au moins une couche de céramique à papier (2) comprenant des faces supérieure et inférieure (2a, 2b), qui présentent une structure de pores composée d’une pluralité de cavités en forme de pores, caractérisé en ce que les cavités en forme de pores de la structure de pores sont, au moins dans la zone des faces supérieure et/ou inférieure (2a, 2b) de la couche de céramique à papier (2), remplies d’un métal ou d’un alliage métallique par utilisation d’un procédé d’infiltration, de telle façon qu’au moins une couche de métallisation (3, 4) avec une épaisseur de couche (d2, d3) entre 0,1 et 10 μm se forme sur les faces supérieure et/ou inférieure. L’invention concerne en outre un procédé pour la fabrication d’un tel substrat ainsi que de modules fabriqués avec celui-ci, en particulier des modules de puissance.
(DE) Die Erfindung betrifft ein Substrat (1) für elektrische Schaltkreise umfassend zumindest eine Papierkeramikschicht (2) mit einer Ober- und Unterseite (2a, 2b), die eine aus einer Vielzahl von porenformigen Hohlräumen bestehende Porenstruktur aufweist, dadurch gekennzeichnet, dass die porenformigen Hohlräume der Porenstruktur zumindest im Bereich der Ober- und/oder Unterseite (2a, 2b) der Papierkeramikschicht (2) unter Verwendung eines Infiltrationsverfahrens derart mit einem Metall oder einer Metalllegierung verfüllt sind, dass sich auf der Ober- und/oder Unterseite (2a, 2b) zumindest eine Metallisierungsschicht (3, 4) mit einer Schichtdicke (d2, d3) zwischen 0,1 bis 10 μιτι ausbildet. Ferner sind Gegenstand der Erfindung ein Verfahren zur Herstellung eines derartigen Substrates sowie daraus hergestellte Module, insbesondere Leistungsmodule.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: German (DE)
Filing Language: German (DE)