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1. (WO2019001753) SUPERCONDUCTOR-SEMICONDUCTOR FABRICATION
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Pub. No.: WO/2019/001753 International Application No.: PCT/EP2017/081038
Publication Date: 03.01.2019 International Filing Date: 30.11.2017
IPC:
H01L 27/18 (2006.01) ,B82Y 10/00 (2011.01) ,G06N 99/00 (2010.01) ,H01L 29/06 (2006.01) ,H01L 39/22 (2006.01) ,H01L 39/24 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
18
including components exhibiting superconductivity
B PERFORMING OPERATIONS; TRANSPORTING
82
NANO-TECHNOLOGY
Y
SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE  OR TREATMENT OF NANO-STRUCTURES
10
Nano-technology for information processing, storage or transmission, e.g. quantum computing or single electron logic
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
99
Subject matter not provided for in other groups of this subclass
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
39
Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
22
Devices comprising a junction of dissimilar materials, e.g. Josephson-effect devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
39
Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
24
Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group H01L39/135
Applicants:
KROGSTRUP JEPPESEN, Peter [DK/DK]; US (KN)
MICROSOFT TECHNOLOGY LICENSING, LLC [US/US]; One Microsoft Way Redmond, Washington 98052-6399, US
Inventors:
KROGSTRUP JEPPESEN, Peter; US
Agent:
WOODHOUSE, Thomas Duncan; PAGE WHITE & FARRER Bedford House John Street London Greater London WC1N 2BF, GB
Priority Data:
1718897.015.11.2017GB
62/527,87530.06.2017US
Title (EN) SUPERCONDUCTOR-SEMICONDUCTOR FABRICATION
(FR) FABRICATION DE SUPRACONDUCTEURS-SEMI-CONDUCTEURS
Abstract:
(EN) A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor- superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.
(FR) Une plate-forme mixte semi-conductrice-supraconductrice selon l'invention est fabriquée par phases. Dans une phase de masquage, un masque diélectrique est formé sur un substrat, de telle sorte que le masque diélectrique quitte une ou plusieurs régions du substrat exposé. Dans une phase de croissance de zone sélective, un matériau semi-conducteur est sélectivement mis à croître sur le substrat dans la ou les régions exposées. Dans une phase de croissance supraconductrice, une couche de matériau supraconducteur est formée, dont au moins une partie est en contact direct avec le matériau semi-conducteur à croissance sélective. La plate-forme supraconductrice semi-conductrice mixte comprend le matériau semi-conducteur à croissance sélective et le matériau supraconducteur en contact direct avec le matériau semi-conducteur à croissance sélective.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)