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1. (WO2019000928) ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, DETECTION METHOD, AND DISPLAY DEVICE
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Pub. No.: WO/2019/000928 International Application No.: PCT/CN2018/073801
Publication Date: 03.01.2019 International Filing Date: 23.01.2018
IPC:
H01L 27/12 (2006.01) ,H01L 23/544 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
544
Marks applied to semiconductor devices, e.g. registration marks, test patterns
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District, Beijing 100015, CN
合肥鑫晟光电科技有限公司 HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国安徽省合肥市 新站区工业园内 Xinzhan Industrial Park, Hefei, Anhui 230012, CN
Inventors:
操彬彬 CAO, Binbin; CN
Agent:
北京天昊联合知识产权代理有限公司 TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; 中国北京市 东城区建国门内大街28号民生金融中心D座10层陈源 Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201710506253.X28.06.2017CN
Title (EN) ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, DETECTION METHOD, AND DISPLAY DEVICE
(FR) SUBSTRAT DE RÉSEAU ET SON PROCÉDÉ DE PRÉPARATION, PROCÉDÉ DE DÉTECTION ET DISPOSITIF D'AFFICHAGE
(ZH) 一种阵列基板及其制备方法、检测方法和显示装置
Abstract:
(EN) Provided is an array substrate and a preparation method therefor, a detection method, and a display device. The array substrate comprises an insulation layer (3), and a first via hole (31) is provided in the insulation layer (3). The array substrate further comprises a detection structure (5), and the detection structure (5) comprises a first conductive structure (21), a second conductive structure (41), and an insulation structure (30) located between the first conductive structure (21) and the second conductive structure (41). The insulation structure (30) is a part of the insulation layer (3). The second conductive structure (41) comprises a first portion (411) and a second portion (412) separated from each other, and the first portion (411) and the second portion (412) separately overlap the first conductive structure (21) in the thickness direction of the array substrate. Moreover, a second via hole (32) is provided in the insulation structure (30) in the part where the first portion (411) overlaps the first conductive structure (21), and a third via hole (33) is provided in the insulation structure (30) in the part where the second portion (412) overlaps the first conductive structure (21).
(FR) L’invention concerne un substrat de réseau et son procédé de préparation, un procédé de détection et un dispositif d’affichage. Le substrat de réseau comprend une couche d'isolation (3), et un premier trou d'interconnexion (31) est disposé dans la couche d'isolation (3). Le substrat de réseau comprend en outre une structure de détection (5), et la structure de détection (5) comprend une première structure conductrice (21), une seconde structure conductrice (41), et une structure d'isolation (30) située entre la première structure conductrice (21) et la seconde structure conductrice (41). La structure d'isolation (30) est une partie de la couche d'isolation (3). La seconde structure conductrice (41) comprend une première partie (411) et une seconde partie (412) séparées l'une de l'autre, et la première partie (411) et la seconde partie (412) chevauchent séparément la première structure conductrice (21) dans la direction de l'épaisseur du substrat de réseau. De plus, un second trou d'interconnexion (32) est disposé dans la structure d'isolation (30) dans la partie où la première partie (411) chevauche la première structure conductrice (21), et un troisième trou d'interconnexion (33) est disposé dans la structure d'isolation (30) dans la partie où la seconde partie (412) chevauche la première structure conductrice (21).
(ZH) 提供一种阵列基板及其制备方法、检测方法和显示装置。阵列基板包括绝缘层(3),绝缘层(3)中设置有第一过孔(31)。阵列基板还包括检测结构(5),检测结构(5)包括第一导电结构(21)和第二导电结构(41)以及位于第一导电结构(21)和第二导电结构(41)之间的绝缘结构(30)。绝缘结构(30)是绝缘层(3)的一部分。第二导电结构(41)包括相互分离的第一部分(411)和第二部分(412),第一部分(411)和第二部分(412)分别与第一导电结构(21)在阵列基板的厚度方向上部分地重合,并且在第一部分(411)和第一导电结构(21)的相互重叠的部分之间的绝缘结构(30)中设置有第二过孔(32),在第二部分(412)和第一导电结构(21)的相互重叠的部分的之间的绝缘结构(30)中设置有第三过孔(33)。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)