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1. (WO2018235843) SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WAFER-ATTACHED STRUCTURE
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Pub. No.: WO/2018/235843 International Application No.: PCT/JP2018/023373
Publication Date: 27.12.2018 International Filing Date: 19.06.2018
IPC:
H01L 21/304 (2006.01) ,B23K 26/53 (2014.01) ,B28D 5/04 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/683 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
[IPC code unknown for B23K 26/53]
B PERFORMING OPERATIONS; TRANSPORTING
28
WORKING CEMENT, CLAY, OR STONE
D
WORKING STONE OR STONE-LIKE MATERIALS
5
Fine working of gems, jewels, crystals, e.g. of semiconductor material; Apparatus therefor
04
by tools other than of rotary type, e.g. reciprocating tools
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
Applicants:
ローム株式会社 ROHM CO., LTD. [JP/JP]; 京都府京都市右京区西院溝崎町21番地 21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto-shi, Kyoto 6158585, JP
Inventors:
明田 正俊 AKETA, Masatoshi; JP
富士 和則 FUJI, Kazunori; JP
Agent:
特許業務法人あい特許事務所 AI ASSOCIATION OF PATENT AND TRADEMARK ATTORNEYS; 大阪府大阪市中央区南本町二丁目6番12号 サンマリオンNBFタワー21階 Sun Mullion NBF Tower, 21st Floor, 6-12, Minamihommachi 2-chome, Chuo-ku, Osaka-shi, Osaka 5410054, JP
Priority Data:
2017-11970419.06.2017JP
Title (EN) SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WAFER-ATTACHED STRUCTURE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEURS ET STRUCTURE FIXÉE À UNE TRANCHE
(JA) 半導体装置の製造方法およびウエハ貼着構造体
Abstract:
(EN) A semiconductor device manufacturing method comprises: a step of preparing a semiconductor wafer source including a first major surface on one side, a second major surface on another side, and a side wall connecting the first major surface and the second major surface; an element forming step of setting a plurality of element forming regions on the first major surface of the semiconductor wafer source, and fabricating semiconductor elements respectively in the plurality of element forming regions; and a wafer source separating step of cutting, after the element forming step, the semiconductor wafer source from a midway portion in the thickness direction of the semiconductor wafer source along a horizontal direction parallel with the first major surface, and thereby separating the semiconductor wafer source into an element-formed wafer and an element-unformed wafer.
(FR) La présente invention concerne un procédé de fabrication d'un dispositif à semi-conducteurs, comprenant : une étape de préparation d'une source de semi-conducteur étagé présentant une première surface principale d'un côté, une seconde surface principale d'un autre côté, et une paroi latérale reliant les première et seconde surfaces principales ; une étape de formation d'éléments consistant à délimiter une pluralité de zones de formation d'éléments sur la première surface principale de la source de semi-conducteur étagé, et à fabriquer des éléments semi-conducteurs respectivement dans la pluralité de zones de formation d'éléments ; et une étape de séparation de source de semi-conducteur étagé consistant à découper, après l'étape de formation d'éléments, la source de semi-conducteur étagé depuis une partie centrale dans le sens de l'épaisseur de la source de semi-conducteur étagé le long d'une direction horizontale parallèle à la première surface principale, et ainsi à diviser la source de semi-conducteur étagé en une tranche formée d'éléments et une tranche non formée d'éléments.
(JA) 半導体装置の製造方法は、一方側の第1主面、他方側の第2主面、ならびに、前記第1主面および前記第2主面を接続する側壁を含む半導体ウエハ源を用意する工程と、前記半導体ウエハ源の前記第1主面に複数の素子形成領域を設定し、前記複数の素子形成領域に半導体素子をそれぞれ作り込む素子形成工程と、前記素子形成工程の後、前記半導体ウエハ源の厚さ方向途中部から前記第1主面に平行な水平方向に沿って前記半導体ウエハ源を切断することにより、前記半導体ウエハ源を素子形成ウエハおよび素子未形成ウエハに分離するウエハ源分離工程と、を含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)