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1. (WO2018235715) MODULE AND METHOD FOR PRODUCING SAME
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Pub. No.: WO/2018/235715 International Application No.: PCT/JP2018/022700
Publication Date: 27.12.2018 International Filing Date: 14.06.2018
IPC:
H01L 21/60 (2006.01) ,H01L 23/12 (2006.01) ,H01L 25/04 (2014.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
松川 喜孝 MATSUKAWA, Yoshitaka; JP
勝部 彰夫 KATSUBE, Akio; JP
Agent:
梁瀬 右司 YANASE, Yuji; JP
丸山 陽介 MARUYAMA, Yosuke; JP
Priority Data:
2017-12016020.06.2017JP
Title (EN) MODULE AND METHOD FOR PRODUCING SAME
(FR) MODULE ET SON PROCÉDÉ DE PRODUCTION
(JA) モジュールおよびその製造方法
Abstract:
(EN) This module 1 is provided with: a substrate 2; a plurality of components 3 which are mounted on an upper surface 2a of the substrate 2; a component 4 which is mounted on a lower surface 2b; a solder ball 5 which is mounted on the lower surface 2b and functions as an external connection terminal; sealing resin layers 6a, 6b which are respectively laminated on the upper surface 2a and the upper surface 2b of the substrate 2; and a shield film 7 which covers the lateral surface and the upper surface of the module 1. The solder ball 5 is partially exposed from a surface 60b of the sealing resin layer 6b; and the exposed portion thereof protrudes from the sealing resin layer 6b. The module 1 is able to be connected to a mother board by connecting the protruding portion of the solder ball 5 to an electrode of the mother board, so that the protruding portion functions as an external connection terminal. There is a void space 9 between the solder ball 5 and the sealing resin layer 6b, so that the stress due to the thermal expansion coefficient difference between the solder and the resin is reduced, thereby suppressing the occurrence of a crack in the solder ball 5.
(FR) L'invention concerne un module 1 qui est pourvu : d'un substrat 2 ; d'une pluralité de composants 3 qui sont montés sur une surface supérieure 2a du substrat 2 ; d'un composant 4 qui est monté sur une surface inférieure 2b ; d'une bille de soudure 5 qui est montée sur la surface inférieure 2b et fonctionne comme un terminal de connexion externe ; de couches de résine d'étanchéité 6a, 6b qui sont respectivement stratifiées sur la surface supérieure 2a et la surface supérieure 2b du substrat 2 ; et d'un film de protection 7 qui recouvre la surface latérale et la surface supérieure du module 1. La bille de soudure 5 est partiellement exposée à partir d'une surface 60b de la couche de résine d'étanchéité 6b ; et la partie exposée de celle-ci fait saillie à partir de la couche de résine d'étanchéité 6b. Le module peut être connecté à une carte mère en connectant la partie en saillie de la bille de soudure à une électrode de la carte mère, de telle sorte que la partie en saillie fonctionne comme un terminal de connexion externe. Il y a un espace vide 9 entre la bille de soudure 5 et la couche de résine d'étanchéité 6b, de telle sorte que la contrainte due à la différence de coefficient de dilatation thermique entre la brasure et la résine est réduite, ce qui permet de supprimer l'apparition d'une fissure dans la bille de soudure 5.
(JA) モジュール1は、基板2と、基板2の上面2aに実装された複数の部品3と、下面2bに実装された部品4と、下面2bに実装され、外部接続端子として機能する半田ボール5と、基板2の上面2aおよび上面2bに積層された封止樹脂層6a、6bと、モジュール1の側面と上面を覆うシールド膜7とを備える。半田ボール5は、封止樹脂層6bの表面60bから一部が露出しており、露出した部分が封止樹脂層6bから突出した形状となっている。半田ボール5の突出部分を外部接続端子としてマザー基板の電極と接続することにより、モジュール1をマザー基板に接続することができる。半田ボール5と封止樹脂層6bとの間には空隙部9があり、半田と樹脂との熱膨張係数の差によるストレスを軽減して、半田ボール5にクラックが発生することを抑制することができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)