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1. (WO2018227086) STRUCTURE, METHOD, AND CIRCUIT FOR ELECTROSTATIC DISCHARGE PROTECTION UTILIZING A RECTIFYING CONTACT
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Pub. No.: WO/2018/227086 International Application No.: PCT/US2018/036658
Publication Date: 13.12.2018 International Filing Date: 08.06.2018
IPC:
H01L 29/872 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
872
Schottky diodes
Applicants:
SILICET, LLC [US/US]; 112 Ellsworth Place Chapel Hill, NC 27516, US
Inventors:
VOLDMAN, Steven, H.; US
Agent:
WRIGHT, James, D.; US
WOLGIN, Neal, B.; US
HIGGINS, David, R.; US
Priority Data:
62/517,11408.06.2017US
Title (EN) STRUCTURE, METHOD, AND CIRCUIT FOR ELECTROSTATIC DISCHARGE PROTECTION UTILIZING A RECTIFYING CONTACT
(FR) STRUCTURE, PROCÉDÉ ET CIRCUIT DE PROTECTION CONTRE LES DÉCHARGES ÉLECTROSTATIQUES À L'AIDE D'UN CONTACT DE REDRESSEMENT
Abstract:
(EN) A device and structure for providing electrostatic discharge (ESD) protection. Schottky barrier diode (SBD) structure comprising a substrate of a first dopant polarity, a well region of a second dopant polarity formed on or within said substrate,, an anode region of a first dopant polarity, a cathode of a second polarity, and a rectifying contact on said anode and/or said cathode, wherein said rectifying contact is formed substantially near the surface of said substrate to provide a rectifying barrier junction between the conducting layer and the semiconductor substrate, providing electrical coupling in said Schottky Barrier diode structure. The disclosure further includes SOI Schottky Barrier polysilicon-bound diodes (also known as Lubistor structures). Additionally, a diode configured SOI dynamic threshold MOSFET with rectifying barrier junctions on the drain or source region.
(FR) L'invention concerne un dispositif et une structure permettant d'assurer une protection contre les décharges électrostatiques (ESD). La structure de diode à barrière de Schottky (SBD) comprend un substrat d'une première polarité de dopant, une région de puits d'une seconde polarité de dopant, formée sur ledit substrat ou dans ce dernier, une région d'anode d'une première polarité de dopant, une cathode d'une seconde polarité et un contact de redressement situé sur ladite anode et/ou sur ladite cathode, ledit contact de redressement étant formé sensiblement à proximité de la surface dudit substrat pour fournir une jonction de barrière de redressement entre la couche conductrice et le substrat semi-conducteur, ce qui produit un couplage électrique dans ladite structure de diode à barrière de Schottky. L'invention concerne en outre des diodes liées par polysilicium à barrière de Schottky de type SSI (également connues sous le nom de structures de Lubistor). De plus, l'invention concerne un MOSFET à seuil dynamique de type SSI configuré par diode comportant des jonctions de barrière de redressement sur la région de drain ou de source.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)