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1. (WO2018226618) FLAT METAL FEATURES FOR MICROELECTRONICS APPLICATIONS
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Pub. No.: WO/2018/226618 International Application No.: PCT/US2018/035947
Publication Date: 13.12.2018 International Filing Date: 05.06.2018
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
INVENSAS CORPORATION [US/US]; 3025 Orchard Parkway San Jose, CA 95134, US
Inventors:
UZOH, Cyprian, Emeka; US
Agent:
LATTIN, Christopher, W.; US
Priority Data:
15/994,43531.05.2018US
62/515,41005.06.2017US
Title (EN) FLAT METAL FEATURES FOR MICROELECTRONICS APPLICATIONS
(FR) ÉLÉMENTS MÉTALLIQUES PLATS POUR DES APPLICATIONS DE MICRO-ÉLECTRONIQUE
Abstract:
(EN) Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical- mechanical planarization (CMP), resulting in very flat damascene features.
(FR) L'invention concerne des métaux plats avancés pour la micro-électronique. Tandis que les procédés classiques créent de grands éléments de damasquinage qui présentent un défaut de bombage provoquant une défaillance dans des dispositifs liés, des exemples de systèmes et de procédés selon l'invention créent de grands éléments de damasquinage qui sont plans. Dans un mode de réalisation, un procédé de recuit crée des gros grains ou de grands cristaux métalliques de cuivre dans de grandes cavités de damasquinage, tandis qu'une couche plus mince de cuivre sur le champ d'un substrat réalise un recuit pour obtenir des grains plus petits de cuivre. Les gros grains de cuivre dans les cavités de damasquinage résistent aux défauts de bombage pendant la planarisation mécano-chimique (PMC), ce qui permet d'obtenir des éléments de damasquinage très plats. Dans un mode de réalisation, des couches de photorésine et des couches d'un second matériau de revêtement peuvent être appliquées de diverses manières pour résister au bombage pendant la planarisation mécano-chimique (PMC), ce qui permet d'obtenir des éléments de damasquinage très plats.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)