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1. (WO2018226511) LOW LEAKAGE FET
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Pub. No.: WO/2018/226511 International Application No.: PCT/US2018/035503
Publication Date: 13.12.2018 International Filing Date: 31.05.2018
Chapter 2 Demand Filed: 16.11.2018
IPC:
H01L 29/423 (2006.01) ,H01L 29/49 (2006.01) ,H01L 29/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Applicants:
PSEMI CORPORATION [US/US]; 9380 Carroll Park Drive San Diego, California 92121, US
Inventors:
PAUL, Abhijeet; US
WILLARD, Simon Edward; US
DUVALLET, Alain; US
Agent:
CASH, Brian J.; US
STEINFL, Alessandro; US
PEREZ, Ronald E.; US
DONG, Lun-Cong; US
XU, Jiancong; US
Priority Data:
15/616,81107.06.2017US
Title (EN) LOW LEAKAGE FET
(FR) TRANSISTOR À EFFET DE CHAMP À FAIBLE FUITE
Abstract:
(EN) FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or "flare" the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.
(FR) La présente invention concerne des conceptions de transistor à effet de champ (TEC) qui présentent une faible fuite en présence du phénomène de transistor de bord. Des modes de réalisation comprennent des conceptions de nTEC dans lesquelles la fonction de travail MF de la structure de grille recouvrant les transistors de bord du nTEC est augmentée en formant des régions d'implant P + supplémentaires à l'intérieur d'au moins une partie de la structure de grille, ce qui permet d'augmenter la tension Vt des transistors de bord à un niveau qui peut dépasser la Vt du canal de conduction central du nTEC. Dans certains modes de réalisation, la structure de grille du nTEC est modifiée pour augmenter ou "évaser" la longueur de canal efficace des transistors de bord par rapport à la longueur du canal de conduction central du TEC. L'invention concerne également d'autres procédés de modification de la fonction de travail MF de la structure de grille recouvrant les transistors de bord. Les procédés peuvent être adaptés à la fabrication de pTECs en inversant ou en substituant des types de matériaux.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)