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1. (WO2018226505) ERROR CORRECTION CALCULATION UPON SERIAL BUS ABORT
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CLAIMS

1. A method for communication in a serial data bus, comprising:

determining at a sending device on the serial data bus a condition whereby a receiver in communication with the sending device over the serial data bus is initiating a termination of data transfer between the sending device and the receiver;

calculating an error check word in the sending device simultaneous with data transfer from the sending device to the receiver; and

taking control of the serial data bus with the sending device after initiation of the termination of data transfer and transmitting the calculated error check word from the sending device to the receiver.

2. The method of claim 1, further comprising:

relinquishing control of the serial data bus by the sending device after transmitting the calculated error check word to the receiver.

3. The method of claim 1, wherein the error check word is configured to avoid contention on the serial data bus with a preamble from the receiver initiating the termination of data transfer.

4. The method of claim 3, wherein configuring the error check word to avoid contention on the serial data bus includes setting at least a first bit of the error check word to a predetermined value to avoid contention.

5. The method of claim 1, wherein calculating the error check word in the sending device simultaneous with data transfer from the sending device to the receiver includes iteratively calculating the error check word with one of each bit or two bits sent by the sending device on the serial data bus.

6. The method of claim 1, wherein taking control of the serial data bus with the sending device includes taking control within a duration of one serial data bus clock cycle.

7. The method of claim 1 , wherein the serial data bus is operated in accordance with a high data rate (HDR) double data rate mode of operation of an I3C protocol.

8. The method of claim 1, wherein terminating data transmission over the serial data bus comprises transmitting an HDR restart pattern on the serial data bus.

9. The method of claim 1, wherein the error check word comprises a cyclic redundancy check (CRC) word.

10. An apparatus, comprising:

a first line driver coupled to a first wire of a multi-wire serial bus;

a second line driver coupled to a second wire of the multi-wire serial bus; and an interface controller configured to:

determine a condition whereby a receiver in communication with the apparatus on the multi-wire serial bus is initiating a termination of data transfer between the apparatus and the receiver;

calculate an error check word simultaneous with data transfer from the apparatus to the receiver; and

take control of the multi-wire serial bus with the apparatus after initiation of the termination of data transfer by the receiver and transmit the calculated error check word to the receiver.

1 1. The apparatus of claim 10, wherein the interface controller is further configured to:

relinquish control of the multi-wire serial bus after transmitting the calculated error check word to the receiver.

12. The apparatus of claim 10, wherein the error check word is configured to avoid contention on the multi-wire serial bus with a preamble from the receiver initiating the termination of data transfer.

13. The apparatus of claim 12, wherein configuring the error check word to avoid contention on the multi-wire serial bus includes setting at least a first bit of the error check word to a predetermined value to avoid contention.

14. The apparatus of claim 10, wherein calculating the error check word in the apparatus simultaneous with data transfer from the apparatus to the receiver includes iteratively calculating the error check word with one of each bit or two bits sent by the apparatus on the multi-wire serial bus.

15. The apparatus of claim 10, wherein taking control of the multi-wire serial bus with the apparatus includes taking control within a duration of one multi-wire serial bus clock cycle.

16. The apparatus of claim 10, wherein the multi-wire serial bus is operated in accordance with a high data rate (HDR) double data rate mode of operation of an I3C protocol.

17. The apparatus of claim 10, wherein terminating data transmission over the multi-wire serial bus comprises transmitting an HDR restart pattern on the multi-wire serial bus.

18. The apparatus of claim 10, wherein the error check word comprises a cyclic redundancy check (CRC) word.

19. An apparatus for communication in a serial data bus, comprising:

means for determining at a sending device on the serial data bus a condition whereby a receiver in communication with the sending device on the serial data bus is initiating a termination of data transfer between the sending device and the receiver; means for calculating an error check word in the sending device simultaneous with data transfer from the sending device to the receiver; and

means for taking control of the serial data bus with the sending device after initiation of the termination of data transfer and transmitting the calculated error check word to the receiver.

20. The apparatus of claim 19, further comprising:

means for relinquishing control of the serial data bus by the sending device after transmitting the calculated error check word to the receiver.

21. The apparatus of claim 19, wherein the error check word is configured to avoid contention on the serial data bus with a preamble from the receiver initiating the termination of data transfer.

22. The apparatus of claim 21 , wherein configuring the error check word to avoid contention on the serial data bus includes setting at least a first bit of the error check word to a predetermined value to avoid contention.

23. The apparatus of claim 19, wherein calculating the error check word in the sending device simultaneous with data transfer from the sending device to the receiver includes iteratively calculating the error check word with one of each bit or two bits sent by the sending device on the serial data bus.

24. The apparatus of claim 19, wherein taking control of the serial data bus with the sending device includes taking control within a duration of one serial data bus clock cycle.

25. The apparatus of claim 19, wherein the serial data bus is operated in accordance with a high data rate (HDR) double data rate mode of operation of an I3C protocol.

26. The apparatus of claim 19, wherein terminating data transmission over the serial data bus comprises transmitting an HDR restart pattern on the serial data bus.

27. The apparatus of claim 19, wherein the error check word comprises a cyclic redundancy check (CRC) word.

28. A method for communication of data over a serial bus, the method comprising: receiving data at a receiving device over the serial bus from a sending device; initiating a termination of data transfer from the sending device prior to completion of data transfer from the sending device; and

receiving a calculated error check word from the sending device on the serial bus after initiating the termination of data transfer by the receiver.

29. The method of claim 28, wherein the receiving device comprises a master device controlling a clock line of the serial bus.

30. The method of claim 28, wherein the error check word comprises a cyclic redundancy check (CRC) word that is calculated by the sending device contemporaneously with transmission of the data by the sending device.