Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018226338) CIRCUITS AND METHODS FOR SPATIAL EQUALIZATION OF IN-BAND SIGNALS IN MIMO RECEIVERS
Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

CIRCUITS AND METHODS FOR SPATIAL EQUALIZATION

OF IN-BAND SIGNALS IN MIMO RECEIVERS

Cross-Reference to Related Application

[0001] This application claims the benefit of United States Patent Application

No. 15/617,828, filed June 8, 2017, which is hereby incorporated by reference herein in its entirety.

Statement Regarding Government Funded Research

[0002] This invention was made with government support under the ACT project awarded by

DARPA and Grant No. FA8650-14-1-7414 awarded by AFMCLO/JAZ. The government has

certain rights in the invention.

Background

[0003] Multiple-Input-Multiple-Output (MJJVIO) technology utilizes multiple antennas to

achieve a multiplication of spectral efficiency in a wireless communication system. In a receiver

array, a coherent summation of signals is carried out to spatially select desired signals with

improved a signal-to-noise ratio (SNR). The spatial diversity gain provided also improves link

reliability.

[0004] In typical MIMO systems, however, RF/analog circuits together with analog-to-

digital converters (ADCs) have to handle the complete array aperture information. In the

presence of strong spatial signals, high instantaneous dynamic range is required, leading to high

power consumption and cost.

[0005] Accordingly, new mechanisms for spatial equalization of in-band signals in MIMO

receivers are desirable.

Summary

[0006] A circuit for spatial equalization of in-band signals, comprising: a first plurality of circuit elements, wherein: each of the first plurality of circuit elements comprising a first variable transconductor, a second variable transconductor, a third variable transconductor, a fourth variable transconductor, an input I, an input Q, an output I, and an output Q; in each of the first plurality of circuit elements: an input of the first variable transconductor is connected to input I and an output of the first variable transconductor is connected to output I; an input of the second variable transconductor is connected to input Q and an output of the second variable

transconductor is connected to output I; an input of the third variable transconductor is connected to input I and an output of the third variable transconductor is connected to output Q; and an input of the fourth variable transconductor is connected to input Q and an output of the fourth variable transconductor is connected to output Q; in at least one of the first plurality of circuit elements: a first variable resistor connects the input I to the output I; and a second variable resistor connects the input Q to the output Q; the input I of each of the first plurality of circuit elements are connected together; and the input Q of each of the first plurality of circuit elements are connected together; a second plurality of circuit elements, wherein: each of the second plurality of circuit elements comprising a first variable transconductor, a second variable transconductor, a third variable transconductor, a fourth variable transconductor, an input I, an input Q, an output I, and an output Q; in each of the second plurality of circuit elements: an input of the first variable transconductor is connected to input I and an output of the first variable transconductor is connected to output I; an input of the second variable transconductor is connected to input Q and an output of the second variable transconductor is connected to output

I; an input of the third variable transconductor is connected to input I and an output of the third variable transconductor is connected to output Q; and an input of the fourth variable

transconductor is connected to input Q and an output of the fourth variable transconductor is connected to output Q; in at least one of the second plurality of circuit elements: a first variable resistor connects the input I to the output I; and a second variable resistor connects the input Q to the output Q; the input I of each of the second plurality of circuit elements are connected together; and the input Q of each of the second plurality of circuit elements are connected together; wherein the output I of a first of the first plurality of circuit elements is connected to the output I of a first of the second plurality of circuit elements; wherein the output I of a second of the first plurality of circuit elements is connected to the output I of a second of the second plurality of circuit elements; wherein the output Q of a first of the first plurality of circuit elements is connected to the output Q of a first of the second plurality of circuit elements; and wherein the output Q of a second of the first plurality of circuit elements is connected to the output Q of a second of the second plurality of circuit elements.

Brief Description of the Drawings

[0007] FIG. 1 shows an example of a schematic for a circuit for spatial equalization of in-band signals in multiple-input-multiple-output (MIMO) receivers in accordance with some embodiments.

[0008] FIG. 2 shows examples of graphs showing impedance values and output voltages of a circuit like that of FIG. 1 in accordance with some embodiments.

[0009] FIG. 3 shows an example of how received signals are processed using a circuit like that of FIG. 1 in accordance with some embodiments.

[0010] FIG. 4 shows an example of a schematic for an integrated circuit for spatial equalization of in-band signals in multiple-input-multiple-output (MIMO) receivers in accordance with some embodiments.

[0011] FIG. 5 is an example of a schematic of a circuit for a transconductance cell incorporating an active load with current-mode beamformer in accordance with some embodiments.

Detailed Description

[0012] Turning to FIG. 1, an example 100 of a circuit for spatial equalization of in-band signals in multiple-input-multiple-output (MIMO) receivers in accordance with some embodiments is illustrated. As shown, circuit 100 includes N passive mixers 114, 116, and 118, N variable resistors RSMALL 120, 122, and 124, N current-mode beamformers 126, 128, and 130, and N output resistors r0 132, 134, and 136. As also shown, the passive mixers can be driven by

N antennas 102, 104, and 106 and N low-noise transconductance amplifiers (LNTAs) 108, 110, and 112, in some embodiments.

[0013] N passive mixers 114, 116, and 118 can be any suitable current-mode passive mixers and any suitable number N of passive mixers can be used in some embodiments. As shown in FIG. 3, each of the passive mixers can be connected to a common local oscillator (LO) in some embodiments.

[0014] N variable resistors RSMALL 120, 122, and 124 can be any suitable variable resistors, can have any suitable range of values, and any suitable number N of variable resistors can be used in some embodiments.

[0015] N current-mode beamformers 126, 128, and 130 can be any suitable current-mode beamformers, and any suitable number N of current-mode beamformers can be used in some embodiments. In some embodiments, the current-mode beamformers (CM-BFs) can be implemented as CM-BF 138 in FIG. 1. As shown, the CM-BFs can each be implements using N variable transconuctance amplifiers 140, 142, and 144 having outputs that are connect to the output of the CM-BF at a node 146.

[0016] N output resistors r0 132, 134, and 136 can be any suitable output resistors, can have any suitable values, and any suitable number N of resistors can be used in some embodiments.

[0017] During operation, the N low-noise transconductance amplifiers (LNTAs) convert the signal voltages sensed by the antennas (which can have
corresponds to the wavelength in free space at the local oscillator (LO) frequency)) to N signal currents, iRF1 2 N, and drive them into the passive mixers, in which these signal currents are downconverted to baseband currents, iB1 2 N.

[0018] To synthesize a desired spatial response, the current-mode beamformers (CM-BFs) sense voltages vB1 2 N and form beams in the current domain, iBF1 2 N.

[0019] Because of currents iB1 2 N and iBF1 2 N, the output voltages across the N output resistors r0 are:

V01, 2, ... , N ~~ (½1, 2, ... , N " ½F1, 2, ... , N) ' Γθ 0)

[0020] While iB1 2 N and r0 are angle-independent, the spatial responses of iBF1 2 N can be suitably synthesized by the CM-BFs, and, as shown in equation (1), the resultant spatial responses of v01 2 N are proportional to the differences between iB1 2 N and iBF1 2 N.

[0021] In the directions of strong signals, beams can be formed in the current domain to exactly match iB1 2 N, leaving output nodes 150, 152, and 154 virtual grounds for the strong signals, or equivalently leading to almost perfect rejection. In the directions of weak signals, notches can be formed in the current domain to null out iBF1 2 N, allowing large output voltage swings (iB1 2 N · r0) at nodes 150, 152, and 154. Flexible CM-BFs with both phase and gain controls allow the independent steering of one or multiple beams/nulls to any suitable directions. If a certain value of rejection ratio is desired, iBF1 2 N can also be synthesized to be a certain proportion of iB1 2 N, therefore allowing the flexible adjustment of notch depths for v01 2 N as well.

[0022] Since v01 2 N are given by equation (1), the baseband voltages vB1 2 N can be easily found by:

VB1, 2, ..., N ~~ V01, 2, ..., N + lBl, 2, ..., N ' ^SMALL

~~ (½1, 2, ..., N " ½F1, 2, ... , N) ' Γθ + ½1, 2, ..., N ' ¾MALL (^)

And the input impedances, ZB1 2 N, can be defined to be:

¾1, 2, ..., N ~~ VB1, 2, ... , N ^ ½1, 2, ..., N

~~ ¾MALL + Γθ ' ~ ½F1, 2, ..., N ^ ½1, 2, ..., N) )

[0023] Equation (3) shows that, in the directions of strong signals, iB1 2 N = iBF1 2 N leads to virtual grounds at output nodes 150, 152, and 154, causing low input impedance ZB1 2 N = ^SMALL- ^n tne directions of weak signals, iBF1 2 N = 0 leads to high input impedance ZB1 2

N = ^-SMALL"1" ro- In ^act' tne sPatial response of the input impedances will follow that of the output voltages, except for a non-zero offset of RSMALL. This offset is provided so that non-zero strong spatial signal voltages can form and be sensed by the CM-BFs.

[0024] Input impedances Zm 2 N can be translated to RF by the passive mixers. This is because low pass filtering impedances at the baseband ports of the mixers result in band pass filtering input impedance profiles, centered around the mixer switching frequency, at the RF ports of the mixers.

[0025] Turning to FIG. 2, example graphs 202, 204, and 206 showing values of

\ , and \v01 2 N \ , respectively, over angles of incidence Θ in accordance with some embodiments are illustrated. As shown in graph 204, the value of
| varies between the values of RSMALL + r0 and RSMALL based on the angle of incidence Θ.

[0026] FIG. 3 shows an example illustration 300 of weak and strong spatial signals 302 being present at the antennas of a MIMO receiver over a variety of angles of incidence Θ, an array pattern 304 formed by v01 2 N, and resulting signal powers at baseband frequency 306 for the weak and strong spatial signals at the inputs to analog-to-digital converters (ADCs) 308, 310, and 312 connected to v01 2 N. As also shown in FIG. 3, a digital beamforming mechanism 314 can be provided at the outputs of the ADCs.

[0027] The CM-BF output current iBFn shown in FIG. 1 on the nth path can be written as:


where Enk is a complex weighting factor from the kth input to the n"1 output. The mathematical method for generating the complex weighting factors Enk can be performed as described in Allen, B. et al., "Adaptive Array Systems Fundamentals and Applications," John Wiley & Sons Ltd., 2005, chapter 4., which is hereby incorporated by references herein in its entirety.

[0028] And according to equation (3), the baseband current iBn on the nth path in the notch direction is given by:


Equations (4) and (5) together with equation (1) lead to:

I 1 W Ι Ϊ * VBk,nOtch \ \

vOn,notch ~ vBn,notch ' T0 ' \ 7, 9m ' k=l I nk ' ~ I I °)

\ SMALL \ vBn,notch )

Matching among elements indicates that vBk notch/vBn notch is frequency-independent. If both gn

and Enk can be implemented in a frequency -independent fashion, v0n notch can be made equal to

zero over infinite bandwidth. Enk can be implemented to be frequency -independent, and gm can be implemented to be largely frequency-independent, due to the voltage-to-current conversion within CMOS device, which is intrinsically frequency-independent as long as there is no reactance, such as gate-to-drain capacitance, in parallel with it.

[0029] Turning to FIG. 4, an example 400 of an integrated circuit (IC) incorporating a circuit for spatial equalization of in-band signals in multiple-input-multiple-output (MFMO) receivers in accordance with some embodiments is illustrated. IC 400 can be implemented in any suitable technology, such as 65nm CMOS process, in some embodiments.

[0030] As shown, IC 400 includes four LNA and mixer circuits 402, 404, 406, and 408, sixteen elements El} 410, four variable gain amplifiers 412, and four buffers 414.

[0031] Each of RF inputs 1-4 in the figure can come from any suitable source, such as a different antenna of a MIMO device. IQ outputs 1-4 can be provided to any suitable devices, such as analog-to-digital converters that convert analog signals from IC 400 to digital signals prior to those signals being provided to a digital beamforming circuit.

[0032] In the illustration of IC 400, the inputs to each element El} (i.e., the arrows on the left of each element) in each row are connected in parallel to the output of the LNA+Mixer in the

same row, and the outputs of each element El} (i.e., the arrows on the bottom of each element) in each column are connected in parallel to the inputs to the VGA in the same column.

[0033] LNA and mixer circuits 402, 404, 406, and 408 can be implemented in any suitable manner, and any suitable number of these circuits can be provided, in some embodiments. For example, the circuits can each be implemented using LNA and mixer circuits 416 in some embodiments.

[0034] As shown, each LNA and mixer circuit 416 can include a low noise amplifier (LNA) 420 and a mixer 422. Any suitable low noise amplifier can be used as LNA 420, and any suitable mixer can be used as mixer 422. For example, in some embodiments, LNA 420 can be implemented using an inverter-based low noise transconductance amplifier (LNTA) using resistive feedback Rf. As another example, in some embodiments, mixer 422 can be

implemented using four single-balanced I/Q passive mixers that are each implemented using a switch that is driven by one of four 25% duty cycle LOs.

[0035] In some embodiments, a differential clock signal at twice the local oscillator (LO) frequency can be generated off-chip. A clock frequency divide-by-two divider 440 can be implemented on-chip to provide a 4-phase LO signal at the desired frequency, which is distributed to the mixers 422. Within each mixer, a digital duty cycle generator 424 reduces the LO signal duty cycle from 50% to slightly less than 25% to ensure non-overlapping switching of the mixer switches. At the mixer output nodes, large shunt metal-insulator-metal (MIM) capacitors (not shown) can be provided to filter out out-of-band signals.

[0036] Elements El} 410 provide the functions of the current-mode beamformers and the resistors RSMALLand r0 of FIGS. 1 and 3. These elements can be implemented in any suitable manner, and any suitable number of the elements can be provided, in some embodiments. For

example, elements El} 410 can each be implemented using example element 418 in some embodiments.

[0037] As shown, each element 418 can include four variable transconductors 426, 428, 430, and 432 and variable resistors R< SMALL 434 and 436 (but only when /'=/'; that is for Ε1 _, E22, E33,

and £"44). As is described below in connection with FIG. 5, variable transconductors 426, 428, 430, and 432 provide the functions of the current mode beamformers and the resistors r0.

[0038] Variable gain amplifiers 412 can be implemented in any suitable manner, and any suitable number of the variable gain amplifiers can be provided, in some embodiments.

[0039] Buffers 414 can be implemented in any suitable manner, and any suitable number of the buffers can be provided, in some embodiments. For example, the buffers can be 50 ohm buffers.

[0040] During operation, the El} element senses the baseband voltage on the j"1 element and converts it to a current on the 1th output with a complex gain of El}. In the four elements where i = j, small resistors RSMALL are inserted in parallel to achieve input impedance modulation.

[0041] Within the El} element, the complex gain El} is achieved by weighting the I-path gm cells 426 and 428 and the Q-path gm cells 430 and 432 differently. That is, as shown in FIG. 4, cell 426 is assigned weight wUj, cell 428 is assigned weight wQ ij, cell 430 is assigned weight wQ and cell 432 is assigned weight Wj The currents at the outputs of cells 426 and 428 are combined to provide Output I, and the currents at the outputs of cells 430 and 432 are combined to provide Output Q.

[0042] The phase shift achieved on Output I is given by:


At the same time, the magnitude control of El , is also embedded, as given by:


[0043] An example 500 of a gm cell that can be used for gm cells 426, 428, 430, and 432 in accordance with some embodiments is shown in FIG. 5. The inputs to the cell are at nodes 502 and 504, and the outputs are at nodes 506 and 508.

[0044] As shown in FIG. 5, each gm cell 500 includes an nMOS differential pair formed by transistors 510 and 512 with tunable resistive degeneration resistor RDEG 514, and bias current sources 516 and 518. The tunable resistive degeneration resistor is used to apply the wi and WQ weighting, and it is controlled by an external controller controlling which of its switches are closed.

[0045] As also shown in FIG. 5, cell 500 includes a shared active load with current-mode beamformer that is connected to output nodes 506 and 508. The shared active load with current-mode beamformer includes a pair of pMOS transistors 520 and 522, an operational amplifier 524, and bias resistors 526 and 528. The pMOS transistors, in parallel with the pMOS transistors of other circuits 500 connected to the same I or Q output, act as resistor r0.

[0046] The mathematical method for generating the complex weightings for the 16 elements 410 (FIG. 4) can be performed as described in Allen, B. et al., "Adaptive Array Systems

Fundamentals and Applications," John Wiley & Sons Ltd., 2005, chapter 4., which is hereby incorporated by references herein in its entirety.

[0047] Although the invention has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of embodiment of the invention can be made without departing from the spirit and scope of the invention, which is limited only by the claims that follow. Features of the disclosed embodiments can be combined and rearranged in various ways.