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1. (WO2018226338) CIRCUITS AND METHODS FOR SPATIAL EQUALIZATION OF IN-BAND SIGNALS IN MIMO RECEIVERS
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Pub. No.:
WO/2018/226338
International Application No.:
PCT/US2018/031413
Publication Date:
13.12.2018
International Filing Date:
07.05.2018
IPC:
H04L 25/03
(2006.01) ,
H03D 7/14
(2006.01) ,
H03F 3/19
(2006.01) ,
H04B 7/0413
(2017.01)
H
ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25
Baseband systems
02
Details
03
Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H
ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
D
DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
7
Transference of modulation from one carrier to another, e.g. frequency-changing
14
Balanced arrangements
H
ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
189
High-frequency amplifiers, e.g. radio frequency amplifiers
19
with semiconductor devices only
[IPC code unknown for H04B 7/0413]
Applicants:
ZHANG, Linxiao
[US/US]; US
KRISHNASWAMY, Harish
[US/US]; US
Inventors:
ZHANG, Linxiao
; US
KRISHNASWAMY, Harish
; US
Agent:
BYRNE, Matthew, T.
; US
HORAN, Nina, R.
; US
POH, Philip, R.
; US
SRINIVASAN, Arthi, G.
; US
Priority Data:
15/617,828
08.06.2017
US
Title
(EN)
CIRCUITS AND METHODS FOR SPATIAL EQUALIZATION OF IN-BAND SIGNALS IN MIMO RECEIVERS
(FR)
CIRCUITS ET PROCÉDÉS D'ÉGALISATION SPATIALE DE SIGNAUX INTRA-BANDE DANS DES RÉCEPTEURS MIMO
Abstract:
(EN)
A circuit for spatial equalization, comprising: circuit elements each comprising four variable transconductors, in each of the circuit elements: an input of a first variable transconductor (VT) is connected to an input I and an output of the first VT is connected to an output I; an input of the second VT is connected to an input Q and an output of the second VT is connected to output I; an input of the third VT is connected to input I and an output of the third VT is connected to the output Q; and an input of the fourth VT is connected to input Q and an output of the fourth VT is connected to output Q; the input I of each of the first plurality of circuit elements are connected together; and the input Q of each of the first plurality of circuit elements are connected together.
(FR)
L'invention concerne un circuit d'égalisation spatiale, comprenant : des éléments de circuit comprenant chacun quatre transconducteurs variables, dans chacun des éléments de circuit : une entrée d'un premier transconducteur variable (VT) est connectée à une entrée I et une sortie du premier VT est connectée à une sortie I; une entrée du deuxième VT est connectée à une entrée Q et une sortie du deuxième VT est connectée à la sortie I; une entrée du troisième VT est connectée à l'entrée I et une sortie du troisième VT est connectée à la sortie Q; et une entrée du quatrième VT est connectée à l'entrée Q et une sortie du quatrième VT est connectée à la sortie Q; les entrées I de chaque élément de la première pluralité d'éléments de circuit sont connectées entre elles; et les entrées Q de chaque élément de la première pluralité d'éléments de circuit sont connectées entre elles.
Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language:
English (
EN
)
Filing Language:
English (
EN
)