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1. (WO2018226299) SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE AND THERMAL CONTROLLER
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CLAIMS

What is claimed is:

1. A computer- implemented method of limiting a control effort on a system comprising a processor having a first cluster having one or more cores and a second cluster having one or more cores, the method comprising:

determining a control effort limit for the processor;

determining a dynamic voltage and frequency scaling (DVFS) state for at least one of the first cluster or second cluster of cores, using the control effort limit and a power map comprising a plurality of DVFS states for each of the first and second cluster of cores, the power map indexed by the control effort limit;

receiving a recommendation that threads scheduled for execution be run on the at least one of the first or second cluster of cores at a DVFS state different than the DVFS state determined using the control effort limit; and

setting the DVFS state of the at least one of the first or second cluster of cores to the DVFS state determined using the control effort limit.

2. The method of claim 1, further comprising:

determining that a total energy dissipated in the processor for a first predetermined period of time is greater than an instantaneous power target for the processor; and

wherein the control effort limit for the processor is determined at least in part on the total energy dissipated in the processor for the first predetermined period.

3. The method of claim 1, further comprising:

reducing the control effort limit in response to determining that an average power consumed by the processor for a second period of time is greater than an average power target for the processor or in response to determining that an average energy dissipated per instruction is greater than a predetermined efficiency threshold for a predetermined period of time.

4. The method of claim 1, further comprising:

monitoring, by the system, a plurality of power zones within the system, wherein each power zone includes a low pass filter having a target power, a filter method, a time constant, a power delta, and the filter method determines a filtered power for the power zone;

reducing the control effort limit in response to determining that, for a power zone in the plurality of power zones:

at a first time, tO, the filtered power for the power zone was less than the power target for the power zone, less a power delta for the power zone; and

at a second time, tl that is later than tO, the filtered power for the power zone exceeds the target power for the power zone.

5. The method of claim 4, further comprising:

continuing to monitor, and determine filtered power for, the power zone that exceeded the target power for the power zone, less the power delta for the power zone; and

continuing to reduce the control effort limit until the filtered power for the power zone tracks the target power for the power zone.

6. The method of claim 1, further comprising:

reducing the control effort limit in response to determining at least one of:

determining that a measured or estimated current limit for the processor is exceeded for a predetermined period of time; and

determining that a number of instructions blocked from execution exceeds a peak throttle rate target for the predetermined period of time, wherein a throttling that blocks the instructions is done by hardware in the system.

7. The method of claim 1, further comprising:

determining a maximum fast die temperature limit for at least one of the first or second cluster of cores; and

determining a maximum control effort for the cluster based at least in part of the maximum fast die temperature and the power map.

8. The method of claim 7, further comprising:

in response to determining that the control effort limit exceeds the maximum control effort limit, setting the control effort limit to the maximum control effort for the processor.

9. The method of claim 1, further comprising:

masking off one or more cores in at least one of the first cluster of cores or the second cluster of cores, such that the masked off cores do not execute a thread; and

limiting a rate at which masking off of one or more cores can occur.

10. The method of claim 1, wherein:

the processor comprises an asymmetric processor;

the first cluster of cores comprises a plurality of performance cores (P-cores); and the second cluster of cores comprises a plurality of efficient cores (E-cores).

11. A non-transitory computer-readable medium having executable instructions stored thereon, that when executed by a processing system comprising at least one hardware processor having a first cluster of one or more cores and a second cluster of one or more cores, the at least one hardware processor coupled to a memory to perform operations comprising a method as in any one of claims 1-10.

12. A processing system comprising:

a processor having at least two core types and at least one core of each core type;

a temperature sensor for each core type;

a scheduler comprising a scheduling queue for each core type;

a closed loop performance controller that determines a control effort for threads of a thread group, and recommends a core type and a dynamic voltage and frequency scaling for threads of the thread group;

a closed loop thermal management system that determines a control effort limit based at least in part on the temperature sensor for each core type; and

wherein the control effort limit is used to limit the core type or DVFS state at which the scheduler will schedule threads in the thread group for execution.

13. The processing system of claim 12, wherein the system comprises a system on a chip.

14. The processing system of claim 12, wherein one or both of the temperature sensors are virtual temperature sensors.

15. A system comprising at least one hardware processor having a first cluster of one or more cores and a second cluster of one or more cores, the at least one hardware processor coupled to a memory programmed with executable instructions that, when executed by the at least one hardware processor, perform operations comprising:

determining a control effort limit for the processor;

determining a dynamic voltage and frequency scaling (DVFS) state for at least one of the first cluster of cores or second cluster of cores, using the control effort limit and a power map comprising a plurality of DVFS states for each of the first and second cluster of cores, the power map indexed by the control effort limit;

receiving a recommendation that threads scheduled for execution be run on the at least one of the first or second cluster of cores at a DVFS state different than the DVFS state determined using the control effort limit; and

setting the DVFS state of the at least one of the first or second cluster of cores to the DVFS state determined using the control effort limit.

16. The system of claim 15, further comprising:

determining that a total energy dissipated in the processor for a first predetermined period of time is greater than an instantaneous power target for the processor; and

wherein the control effort limit for the processor is determined at least in part on the total energy dissipated in the processor for the first predetermined period.

17. The system of claim 15, further comprising:

reducing the control effort limit in response to determining that an average power consumed by the processor for a second period of time is greater than an average power target for the processor or

determining that an average energy dissipated per instruction is greater than a predetermined efficiency threshold for a predetermined period of time.

18. The system of claim 15, further comprising:

monitoring, by the system, a plurality of power zones within the system, wherein each power zone includes a low pass filter having a target power, a filter method, a time constant, a power delta, and the filter method determines a filtered power for the power zone;

reducing the control effort limit in response to determining that, for a power zone in the plurality of power zones:

at a first time, tO, the filtered power for the power zone was less than the power target for the power zone, less the power delta for the power zone; and

at a second time, tl that is later than tO, the filtered power for the power zone exceeds the target power for the power zone, less the power delta for the power zone.

19. The system of claim 18, further comprising:

continuing to monitor, and determine filtered power for, the power zone that exceeded the target power for the power zone, less the delta for the power zone; and

continuing to reduce the control effort limit until the filtered power for the power zone tracks the target power for the power zone.

20. The system of claim 15, further comprising:

reducing the control effort limit in response to determining at least one of:

determining that a measured or estimated current limit for the processor is exceeded for a predetermined period of time; and

determining that a number of instructions blocked from execution exceeds a peak throttle rate target for the predetermined period of time, wherein a throttling that blocks the instructions is done by hardware in the system.

21. The system of claim 15, further comprising:

determining a maximum fast die temperature limit for at least one of the first or second cluster of cores; and

determining a maximum control effort for the cluster based at least in part of the maximum fast die temperature and the power map.

22. The system of claim 21, further comprising:

in response to determining that the control effort limit exceeds the maximum control effort limit, setting the control effort limit to the maximum control effort for the processor.

23. The system of claim 15, further comprising:

masking off one or more cores in at least one of the first cluster of cores or the second clusters of cores, such that the masked off cores do not execute a thread; and

limiting a rate at which masking off of one or more cores can occur.

24. The system of claim 23, wherein:

the processor comprises an asymmetric processor;

the first cluster of cores comprises a plurality of performance cores (P-cores); and the second cluster of cores comprises a plurality of efficient cores (E-cores).