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1. (WO2018226299) SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE AND THERMAL CONTROLLER
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Pub. No.:
WO/2018/226299
International Application No.:
PCT/US2018/024807
Publication Date:
13.12.2018
International Filing Date:
28.03.2018
Chapter 2 Demand Filed:
02.10.2018
IPC:
G06F 1/32
(2006.01)
G
PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
32
Means for saving power
Applicants:
APPLE INC.
[US/US]; One Apple Park Way Cupertino, California 95014, US
Inventors:
ANDRUS, Jeremy, C.
; US
DORSEY, John, G.
; US
MAGEE, James, M.
; US
CHIMENE, Daniel, A.
; US
DE LA CROPTE DE CHANTERAC, Cyril
; US
HINCH, Bryan, R.
; US
VENKATARAMAN, Aditya
; US
DOROFEEV, Andrei
; US
GAMBLE, Nigel, R.
; US
BLAINE, Russell, A.
; US
PISTOL, Constantin
; US
ISMAIL, James, S.
; US
Agent:
HAMILTON, Howard, S.
; US
Priority Data:
15/870,760
12.01.2018
US
62/514,930
04.06.2017
US
Title
(EN)
SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE AND THERMAL CONTROLLER
(FR)
ORDONNANCEUR POUR ARCHITECTURE AMP UTILISANT UN DISPOSITIF DE COMMANDE DE PERFORMANCES ET THERMIQUE EN BOUCLE FERMÉE
Abstract:
(EN)
Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
(FR)
L'invention concerne des systèmes et des procédés d'ordonnancement de fils sur un processeur qui comprend au moins deux types de cœur différents, tel qu'un système de multitraitement asymétrique (AMP). Chaque type de cœur peut fonctionner dans une pluralité d'états d'ajustement dynamique de tension et de fréquence (DVFS). Des fils issus d'une pluralité de processus peuvent être regroupés en groupes de fils. Des métriques d'exécution sont accumulées pour des fils d'un groupe de fils et introduites dans une pluralité de dispositifs de commande accordables pour le groupe de fils. Un système de commande de performances en boucle fermée (CLPC) détermine un effort de commande pour le groupe de fils et fait correspondre l'effort de commande à un type de cœur et à un état DVFS recommandés. Un système de gestion thermique et de puissance en boucle fermée peut limiter l'effort de commande déterminé par le CLPC pour un groupe de fils, et limiter la puissance, le type de cœur et les états DVFS pour le système. Des interruptions différées peuvent être utilisées pour augmenter les performances.
Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language:
English (
EN
)
Filing Language:
English (
EN
)