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1. (WO2018225822) METHOD FOR PRODUCING THIN FILM TRANSISTOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/225822 International Application No.: PCT/JP2018/021876
Publication Date: 13.12.2018 International Filing Date: 07.06.2018
IPC:
H01L 21/336 (2006.01) ,C23C 14/08 (2006.01) ,C23C 14/34 (2006.01) ,H01L 21/363 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
06
characterised by the coating material
08
Oxides
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
22
characterised by the process of coating
34
Sputtering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
36
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
363
using physical deposition, e.g. vacuum deposition, sputtering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
日新電機株式会社 NISSIN ELECTRIC CO., LTD. [JP/JP]; 京都府京都市右京区梅津高畝町47番地 47, Umezu Takase-cho, Ukyo-ku, Kyoto-shi, Kyoto 6158686, JP
Inventors:
松尾 大輔 MATSUO, Daisuke; JP
安東 靖典 ANDO, Yasunori; JP
瀬戸口 佳孝 SETOGUCHI, Yoshitaka; JP
岸田 茂明 KISHIDA, Shigeaki; JP
Agent:
西村 竜平 NISHIMURA, Ryuhei; JP
Priority Data:
2017-11301407.06.2017JP
Title (EN) METHOD FOR PRODUCING THIN FILM TRANSISTOR
(FR) PROCÉDÉ PERMETTANT DE PRODUIRE UN TRANSISTOR À COUCHES MINCES
(JA) 薄膜トランジスタの製造方法
Abstract:
(EN) A method for producing a thin film transistor that has a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode on a substrate. This method for producing a thin film transistor comprises a step for forming the oxide semiconductor layer on the gate insulating layer by sputtering a target with use of a plasma. The step for forming an oxide semiconductor layer comprises: a first film formation step wherein sputtering is carried out by supplying, as the sputtering gas, an argon gas only; and a second film formation step wherein sputtering is carried out by supplying, as the sputtering gas, a mixed gas of an argon gas and an oxygen gas. This method for producing a thin film transistor is configured such that the bias voltage applied to the target is a negative voltage of -1 kV or more.
(FR) La présente invention concerne un procédé permettant de produire un transistor à couches minces qui comporte une électrode de grille, une couche d'isolation de grille, une couche semi-conductrice d'oxyde, une électrode de source et une électrode de drain sur un substrat. Ce procédé permettant de produire un transistor à couches minces comprend une étape consistant à former la couche semi-conductrice d'oxyde sur la couche d'isolation de grille par pulvérisation d'une cible à l'aide d'un plasma. L'étape consistant à former une couche semi-conductrice d'oxyde comprend : une première étape de formation de film au cours de laquelle une pulvérisation est effectuée en fournissant, en tant que gaz de pulvérisation, de l'argon gazeux uniquement ; et une seconde étape de formation de film au cours de laquelle la pulvérisation est effectuée en fournissant, en tant que gaz de pulvérisation, un gaz mixte composé de l'argon gazeux et de l'oxygène gazeux. Ce procédé permettant de produire un transistor à couches minces est configuré de telle sorte que la tension de polarisation appliquée à la cible soit une tension négative égale ou supérieure à -1 kV.
(JA) 基板上に、ゲート電極と、ゲート絶縁層と、酸化物半導体層と、ソース電極と、ドレイン電極とを有する薄膜トランジスタの製造方法であって、プラズマを用いてターゲットをスパッタリングすることにより、前記ゲート絶縁層の上に酸化物半導体層を形成する工程を含み、前記酸化物半導体層を形成する工程は、スパッタリングガスとしてアルゴンガスのみを供給してスパッタリングを行う第1成膜工程と、スパッタリングガスとしてアルゴンガスと酸素ガスの混合ガスを供給してスパッタリングを行う第2成膜工程とを含み、前記ターゲットに印加するバイアス電圧が-1kV以上の負電圧である、薄膜トランジスタの製造方法である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)