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1. (WO2018225809) CERAMIC CIRCUIT SUBSTRATE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/225809 International Application No.: PCT/JP2018/021810
Publication Date: 13.12.2018 International Filing Date: 07.06.2018
IPC:
H05K 3/18 (2006.01) ,B23K 1/00 (2006.01) ,C23C 18/42 (2006.01) ,H01L 23/13 (2006.01) ,H01L 23/36 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01) ,H05K 3/32 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
10
in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
18
using precipitation techniques to apply the conductive material
B PERFORMING OPERATIONS; TRANSPORTING
23
MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
K
SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
1
Soldering, e.g. brazing, or unsoldering
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
18
Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
16
by reduction or substitution, i.e. electroless plating
31
Coating with metals
42
Coating with noble metals
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
Applicants:
デンカ株式会社 DENKA COMPANY LIMITED [JP/JP]; 東京都中央区日本橋室町二丁目1番1号 1-1, Nihonbashi-Muromachi 2-chome, Chuo-ku, Tokyo 1038338, JP
Inventors:
青野 良太 AONO Ryota; JP
中原 史博 NAKAHARA Fumihiro; JP
西村 浩二 NISHIMURA Kouji; JP
津川 優太 TSUGAWA Yuta; JP
Agent:
園田・小林特許業務法人 SONODA & KOBAYASHI INTELLECTUAL PROPERTY LAW; 東京都新宿区西新宿二丁目1番1号 新宿三井ビル34階 34th Floor, Shinjuku Mitsui Building, 1-1, Nishi-Shinjuku 2-chome, Shinjuku-ku, Tokyo 1630434, JP
Priority Data:
2017-11394609.06.2017JP
Title (EN) CERAMIC CIRCUIT SUBSTRATE
(FR) SUBSTRAT DE CIRCUIT EN CÉRAMIQUE
(JA) セラミックス回路基板
Abstract:
(EN) [Problem] To obtain a ceramic circuit substrate that is suitable for a silver nanoparticle junction in a semiconductor element and has excellent adhesion to a power module sealing resin. [Solution] Provided is a ceramic circuit substrate which is formed by bonding a copper plate, via a brazing material, onto both main surfaces of a ceramic substrate comprising aluminum nitride or silicon nitride and in which the copper plate on at least one main surface is silver-plated, the ceramic circuit substrate being characterized in that: the lateral sides of the copper plates are not silver-plated; the silver plating has a thickness of 0.1-1.5 μm; and the sliver-plated circuit substrate has an arithmetic mean surface roughness Ra of 0.1-1.5 μm.
(FR) L'objet de la présente invention est d'obtenir un substrat de circuit en céramique qui est approprié pour une jonction de nanoparticules d'argent dans un élément semi-conducteur et a une excellente adhérence à une résine d'étanchéité de module d'alimentation. La solution selon l'invention porte sur un substrat de circuit en céramique qui est formé par liaison d'une plaque de cuivre, par l'intermédiaire d'un matériau de brasage, sur les deux surfaces principales d'un substrat en céramique comprenant du nitrure d'aluminium ou du nitrure de silicium et dans lequel la plaque de cuivre sur au moins une surface principale est argentée, le substrat de circuit en céramique étant caractérisé en ce que : les côtés latéraux des plaques de cuivre ne sont pas argentés ; le dépôt d'argent a une épaisseur de 0,1 à 1,5 µm ; et le substrat de circuit argenté a une rugosité de surface moyenne arithmétique Ra de 0,1 à 1,5 µm.
(JA) 【課題】半導体素子の銀ナノ粒子接合に好適であり、パワーモジュール封止樹脂との密着性に優れるセラミックス回路基板を得ること。 【解決手段】窒化アルミニウムまたは窒化珪素を用いてなるセラミックス基板の両主面に、銅板がろう材を介して接合され、少なくとも一方の主面の銅板上に銀めっきが施されたセラミックス回路基板であって、銅板側面は銀めっきが施されておらず、銀めっきの厚みが0.1μmから1.5μmであり、銀めっき後の回路基板の表面粗さの算術平均粗さRaが0.1μmから1.5μmであることを特徴とするセラミックス回路基板。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)