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1. (WO2018225690) ACTIVE-MATRIX SUBSTRATE AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/225690 International Application No.: PCT/JP2018/021389
Publication Date: 13.12.2018 International Filing Date: 04.06.2018
IPC:
G09F 9/30 (2006.01) ,G02F 1/1368 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 27/088 (2006.01) ,H01L 29/786 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
武田 悠二郎 TAKEDA Yujiro; --
松木薗 広志 MATSUKIZONO Hiroshi; --
織田 明博 ODA Akihiro; --
村重 正悟 MURASHIGE Shogo; --
田中 耕平 TANAKA Kohhei; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2017-11326808.06.2017JP
Title (EN) ACTIVE-MATRIX SUBSTRATE AND DISPLAY DEVICE
(FR) SUBSTRAT À MATRICE ACTIVE ET DISPOSITIF D'AFFICHAGE
(JA) アクティブマトリクス基板および表示装置
Abstract:
(EN) An active-matrix substrate according to an embodiment of the present invention is provided with a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT has: a lower gate electrode provided on the substrate; a gate insulating layer covering the lower gate electrode; an oxide semiconductor layer arranged on the gate insulating layer; a source electrode in contact with the source contact region of the oxide semiconductor layer; a drain electrode in contact with the drain contact region of the oxide semiconductor layer; an insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode; and an upper gate electrode provided on the insulating layer. When seen from the normal direction of the substrate, the upper gate electrode does not overlap a first electrode that is one of the source electrode and the drain electrode, and a second electrode that is the other of the source electrode and the drain electrode does not overlap the lower gate electrode.
(FR) La présente invention concerne un substrat à matrice active qui est pourvu d'un substrat et d'une pluralité de TFT à semi-conducteur à oxyde reposant sur le substrat. Chaque TFT à semi-conducteur à oxyde comprend : une électrode de grille inférieure disposée sur le substrat ; une couche d'isolation de grille recouvrant l'électrode de grille inférieure ; une couche semi-conductrice d'oxyde disposée sur la couche d'isolation de grille ; une électrode de source en contact avec la région de contact de source de la couche semi-conductrice d'oxyde ; une électrode de drain en contact avec la région de contact de drain de la couche semi-conductrice d'oxyde ; une couche isolante recouvrant la couche semi-conductrice d'oxyde, l'électrode de source et l'électrode de drain ; et une électrode de grille supérieure disposée sur la couche isolante. Lorsqu'elle est vue depuis la direction normale du substrat, l'électrode de grille supérieure ne chevauche pas une première électrode qui est l'une de l'électrode de source et de l'électrode de drain, et une seconde électrode qui est l'autre de l'électrode de source et de l'électrode de drain ne chevauche pas l'électrode de grille inférieure.
(JA) 本発明の実施形態によるアクティブマトリクス基板は、基板と、基板に支持された複数の酸化物半導体TFTとを備える。各酸化物半導体TFTは、基板上に設けられた下部ゲート電極と、下部ゲート電極を覆うゲート絶縁層と、ゲート絶縁層上に配置された酸化物半導体層と、酸化物半導体層のソースコンタクト領域に接するソース電極と、酸化物半導体層のドレインコンタクト領域に接するドレイン電極と、酸化物半導体層、ソース電極およびドレイン電極を覆う絶縁層と、絶縁層上に設けられた上部ゲート電極とを有する。基板の法線方向から見たとき、上部ゲート電極は、ソース電極およびドレイン電極のうちの一方である第1電極に重なっておらず、且つ、ソース電極およびドレイン電極のうちの他方である第2電極は、下部ゲート電極に重なっていない。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)