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1. (WO2018225203) DISPLAY DEVICE AND METHOD FOR DRIVING SAME
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Pub. No.: WO/2018/225203 International Application No.: PCT/JP2017/021257
Publication Date: 13.12.2018 International Filing Date: 08.06.2017
IPC:
G09G 3/3233 (2016.01) ,G09G 3/20 (2006.01) ,G09G 3/30 (2006.01) ,G09G 3/3208 (2016.01)
[IPC code unknown for G09G 3/3233]
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
22
using controlled light sources
30
using electroluminescent panels
[IPC code unknown for G09G 3/3208]
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
小林 史幸 KOBAYASHI, Fumiyuki; --
Agent:
島田 明宏 SHIMADA, Akihiro; JP
川原 健児 KAWAHARA, Kenji; JP
奥田 邦廣 OKUDA, Kunihiro; JP
河本 悟 KAWAMOTO, Satoru; JP
Priority Data:
Title (EN) DISPLAY DEVICE AND METHOD FOR DRIVING SAME
(FR) DISPOSITIF D’AFFICHAGE ET SON PROCÉDÉ D'ATTAQUE
(JA) 表示装置およびその駆動方法
Abstract:
(EN) The pixel circuit according to the present invention includes: an electrooptical element; a drive transistor; a first transistor, wherein a first conduction terminal is connected to a control terminal of the drive transistor, and a control terminal is connected to a first node; and a second transistor, wherein a first conduction terminal is connected to a second conduction terminal of the first transistor, an initialization voltage is applied to a second conduction terminal, and a control terminal is connected to the first node. A connection point between the first and second transistors is connected to an anode terminal of the electrooptical element, and a cathode terminal of the electrooptical element is connected to second power supply wiring. Consequently, the voltage of the control terminal of the drive transistor, and the anode voltage of the electrooptical element are initialized with a circuit amount that is less than that in conventional cases.
(FR) La présente invention concerne un circuit de pixel comprenant : un élément électro-optique ; un transistor d'attaque ; un premier transistor, une première borne de conduction étant connectée à une borne de commande du transistor d'attaque, et une borne de commande étant connectée à un premier nœud ; et un second transistor, une première borne de conduction étant connectée à une seconde borne de conduction du premier transistor, une tension d'initialisation étant appliquée à une seconde borne de conduction, et une borne de commande étant connectée au premier nœud. Un point de connexion entre les premier et second transistors est connecté à une borne d'anode de l'élément électro-optique, et une borne de cathode de l'élément électro-optique est connectée à un second câblage d'alimentation électrique. Par conséquent, la tension de la borne de commande du transistor d'attaque et la tension d'anode de l'élément électro-optique sont initialisées à l'aide d'une quantité de circuit qui est inférieure à celle que l'on trouve dans des cas classiques.
(JA) 画素回路は、電気光学素子と、駆動トランジスタと、第1導通端子が駆動トランジスタの制御端子に接続され、制御端子が第1ノードに接続された第1トランジスタと、第1導通端子が第1トランジスタの第2導通端子に接続され、第2導通端子に初期化電圧が印加され、制御端子が第1ノードに接続された第2トランジスタとを含む。第1および第2トランジスタの接続点を電気光学素子のアノード端子に接続し、電気光学素子のカソード端子を第2電源配線に接続する。これにより、駆動トランジスタの制御端子の電圧と電気光学素子のアノード電圧とを従来よりも少ない回路量で初期化する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)