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1. (WO2018225136) SOFT ERROR INSPECTION METHOD, SOFT ERROR INSPECTION DEVICE, AND SOFT ERROR INSPECTION SYSTEM
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Pub. No.: WO/2018/225136 International Application No.: PCT/JP2017/020863
Publication Date: 13.12.2018 International Filing Date: 05.06.2017
IPC:
G01R 31/30 (2006.01) ,G01R 31/26 (2014.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
30
Marginal testing, e.g. by varying supply voltage
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26
Testing of individual semiconductor devices
Applicants:
富士通株式会社 FUJITSU LIMITED [JP/JP]; 神奈川県川崎市中原区上小田中4丁目1番1号 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588, JP
Inventors:
添田 武志 SOEDA, Takeshi; JP
Agent:
伊東 忠重 ITOH, Tadashige; JP
伊東 忠彦 ITOH, Tadahiko; JP
Priority Data:
Title (EN) SOFT ERROR INSPECTION METHOD, SOFT ERROR INSPECTION DEVICE, AND SOFT ERROR INSPECTION SYSTEM
(FR) PROCÉDÉ D'INSPECTION D'ERREUR LOGICIELLE, DISPOSITIF D'INSPECTION D'ERREUR LOGICIELLE ET SYSTÈME D'INSPECTION D'ERREUR LOGICIELLE
(JA) ソフトエラー検査方法、ソフトエラー検査装置及びソフトエラー検査システム
Abstract:
(EN) The present invention solves the problem of related art by providing a soft error inspection method for a semiconductor device, which is characterized by having a step for irradiating laser light or an electron beam onto a semiconductor device so as to scan the semiconductor device and a step for measuring and storing the bit flip time for each area of the semiconductor device irradiated with the laser light or electron beam.
(FR) La présente invention permet de résoudre le problème de l'état de la technique par la fourniture d'un procédé d'inspection d'erreur logicielle d'un dispositif à semi-conducteur, caractérisé en ce qu'il consiste à exposer un dispositif à semi-conducteur à une lumière laser ou un faisceau d'électrons de manière à balayer le dispositif à semi-conducteur et à mesurer et à mémoriser le temps de basculement binaire pour chaque zone du dispositif à semi-conducteur exposé à la lumière laser ou le faisceau d'électrons.
(JA) 半導体デバイスにおけるソフトエラー検査方法において、前記半導体デバイスにレーザ光または電子線を照射し走査する工程と、前記半導体デバイスの前記レーザ光または前記電子線が照射されている領域ごとにビット反転の時間を測定し記憶する工程と、を有することを特徴とするソフトエラー検査方法により上記課題を解決する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)