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1. (WO2018224009) ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL
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Pub. No.: WO/2018/224009 International Application No.: PCT/CN2018/090278
Publication Date: 13.12.2018 International Filing Date: 07.06.2018
IPC:
G02F 1/1343 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1343
Electrodes
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
刘冬妮 LIU, Dongni; CN
方正 FANG, Zheng; CN
陈小川 CHEN, Xiaochuan; CN
杨盛际 YANG, Shengji; CN
Agent:
北京市柳沈律师事务所 LIU, SHEN & ASSOCIATES; 中国北京市 海淀区彩和坊路10号1号楼10层 10th Floor, Building 1, 10 Caihefang Road, Haidian District Beijing 100080, CN
Priority Data:
201710434369.709.06.2017CN
Title (EN) ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL
(FR) SUBSTRAT DE RÉSEAU ET PROCÉDÉ DE FABRICATION ASSOCIÉ, ET PANNEAU D'AFFICHAGE
(ZH) 阵列基板及其制造方法、显示面板
Abstract:
(EN) An array substrate (10) comprises: multiple gate lines (101), multiple data lines (102), and multiple pixel units (103) defined by the intersection of the gate lines (101) and the data lines (102). The multiple pixel units (103) are arranged in an array. Each of the pixel units (103) comprises: a first pixel electrode (1032) and a second pixel electrode (1033) insulated from each other, wherein the first pixel electrode (1032) and the second pixel electrode (1033) are arranged along an extending direction of the multiple data lines (102); and a first thin film transistor (1034) connected to the first pixel electrode (1032) and a second thin film transistor (1035) connected to the second pixel electrode (1033), wherein a boundary (1031) between the first pixel electrode (1032) and the second pixel electrode (1033) and an extending direction of the gate lines (101) form a preset included angle, and the first thin film transistor (1033) and the second thin film transistor (1035) can load voltage signals of different polarities to the first pixel electrode (1032) and the second pixel electrode (1033) respectively. A manufacturing method of the array substrate and a display panel are also disclosed.
(FR) Selon la présente invention, un substrat de réseau (10) comprend : de multiples lignes de grille (101), de multiples lignes de données (102), et de multiples unités de pixel (103) définies par l'intersection des lignes de grille (101) et des lignes de données (102). Les multiples unités de pixel (103) sont agencées en un réseau. Chacune des unités de pixel (103) comprend : une première électrode de pixel (1032) et une seconde électrode de pixel (1033) isolées l'une de l'autre, la première électrode de pixel (1032) et la seconde électrode de pixel (1033) étant agencées le long d'une direction d'extension des multiples lignes de données (102) ; et un premier transistor à film mince (1034) connecté à la première électrode de pixel (1032) et un second transistor à film mince (1035) connecté à la seconde électrode de pixel (1033), une limite (1031) entre la première électrode de pixel (1032) et la seconde électrode de pixel (1033) et une direction d'extension des lignes de grille (101) formant un angle inclus prédéfini, et le premier transistor à film mince (1033) et le second transistor à film mince (1035) peuvent charger des signaux de tension de différentes polarités à la première électrode de pixel (1032) et à la seconde électrode de pixel (1033) respectivement. L'invention concerne également un procédé de fabrication du substrat de réseau et un panneau d'affichage.
(ZH) 一种阵列基板(10),包括:多条栅线(101)、多条数据线(102)、及由所述栅线(101)和所述数据线(102)交叉限定的多个像素单元(103),所述多个像素单元(103)呈阵列排布;每个所述像素单元(103)包括:相互绝缘的第一像素电极(1032)和第二像素电极(1033),所述第一像素电极(1032)和所述第二像素电极(1033)沿所述多条数据线(102)的延伸方向布置,以及与所述第一像素电极(1032)连接的第一薄膜晶体管(1034),与所述第二像素电极(1033)连接的第二薄膜晶体管(1035),所述第一像素电极(1032)和所述第二像素电极(1033)之间的边界(1031)与所述栅线(101)的延伸方向呈预设夹角;第一薄膜晶体管(1033)和第二薄膜晶体管(1035)能够分别为第一像素电极(1032)和第二像素电极(1033)加载不同极性的电压信号。还公开了一种制造该阵列基板的方法以及一种显示面板。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)