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1. (WO2018223967) SEMICONDUCTOR DEVICE STRUCTURES AND FABRICATION METHODS THEREOF
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Considered void 17.12.2018


Pub. No.: WO/2018/223967 International Application No.: PCT/CN2018/089987
Publication Date: 13.12.2018 International Filing Date: 05.06.2018
IPC:
H01L 21/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
Applicants:
CHANGXIN MEMORY TECHNOLOGIES, INC. [CN/CN]; Room 630, Haiheng Building, No. 6, Cuiwei Road, Economic and Technological Development Zone, Hefei, Anhui 230000, CN
Inventors:
ZHU, Rongfu; CN
Agent:
METIS IP (CHENGDU) LLC; No. 846 South Tianfu Road, Tianfu Innovation Center Chengdu, Sichuan 610213, CN
Priority Data:
201710411778.505.06.2017CN
Title (EN) SEMICONDUCTOR DEVICE STRUCTURES AND FABRICATION METHODS THEREOF
(FR) STRUCTURES DE DISPOSITIF À SEMI-CONDUCTEUR ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) Semiconductor device structures and fabrication methods thereof are provided. The fabrication method may include providing a silicon layer (110); forming an intermediate layer on the silicon layer (120), wherein the intermediate layer includes a first metal layer, made of a first metal and formed on an upper surface of the silicon layer; and a second metal layer, made of a second metal and formed on the first metal layer; forming an insulating layer on an upper surface of the intermediate layer under a predetermined temperature (130), thereby at least partial of the first metal layer and at least partial of the silicon layer together forming a first metal silicide layer on the silicon layer.
(FR) L'invention concerne des structures de dispositif à semi-conducteur et leurs procédés de fabrication. Le procédé de fabrication peut comprendre la fourniture d'une couche de silicium (110); la formation d'une couche intermédiaire sur la couche de silicium (120), la couche intermédiaire comprenant une première couche métallique, constituée d'un premier métal et formée sur une surface supérieure de la couche de silicium; et une seconde couche métallique, constituée d'un second métal et formée sur la première couche métallique; la formation d'une couche d'isolation sur une surface supérieure de la couche intermédiaire à une température prédéterminée (130), permettant ainsi au moins une partie de la première couche métallique et au moins une partie de la couche de silicium de former ensemble une première couche de siliciure métallique sur la couche de silicium.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)