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1. (WO2018223317) CHIP PACKAGING STRUCTURE AND METHOD, AND TERMINAL DEVICE
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Pub. No.: WO/2018/223317 International Application No.: PCT/CN2017/087452
Publication Date: 13.12.2018 International Filing Date: 07.06.2017
IPC:
H01L 27/146 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
深圳市汇顶科技股份有限公司 SHENZHEN GOODIX TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 福田保税区腾飞工业大厦B座13层 Floor 13, Phase B Tengfei Industrial Building Futian Free Trade Zone Shenzhen, Guangdong 518045, CN
Inventors:
董昊翔 DONG, Haoxiang; CN
韦亚 WEI, Ya; CN
Agent:
北京龙双利达知识产权代理有限公司 LONGSUN LEAD IP LTD.; 中国北京市海淀区北清路68号院3号楼101 Rm.101, Building 3 No. 68 Beiqing Road, Haidian District Beijing 100094, CN
Priority Data:
Title (EN) CHIP PACKAGING STRUCTURE AND METHOD, AND TERMINAL DEVICE
(FR) STRUCTURE ET PROCÉDÉ DE MISE SOUS BOÎTIER DE PUCE, ET DISPOSITIF TERMINAL
(ZH) 芯片封装结构、方法和终端设备
Abstract:
(EN) A chip packaging structure and method, and a terminal device, wherein same can reduce the thickness and size of packaging. The chip packaging structure (10) comprises: an optical sensing chip (11), comprising a first surface (111) and a second surface (112), wherein a first bonding pad (13) is provided on the first surface, a connection end (15) is provided on the second surface, the first bonding pad is electrically connected to the connection end, and the connection end is used for electrical connection between the chip packaging structure and the outside world; and an optical path modulation structure (12), wherein same is provided above the first surface for the incidence of an optical signal reflected from a human finger, after being subjected to optical path modulation, on the first surface, or for emitting an optical signal emitted from the first surface, after being subjected to optical path modulation, to the human finger.
(FR) L'invention concerne une structure et un procédé de mise sous boîtier de puce, et un dispositif terminal, ces derniers permettant de réduire l'épaisseur et la taille du boîtier. La structure de mise sous boîtier de puce (10) comprend : une puce de détection optique (11), comprenant une première surface (111) et une seconde surface (112), une première pastille de connexion (13) étant disposée sur la première surface, une extrémité de connexion (15) étant disposée sur la seconde surface, la première pastille de connexion étant électriquement connectée à l'extrémité de connexion, et l'extrémité de connexion servant à établir une connexion électrique entre la structure de mise sous boîtier de puce et le monde extérieur ; et une structure de modulation de trajet optique (12), cette dernière étant disposée au-dessus de la première surface à des fins d'incidence d'un signal optique réfléchi par un doigt humain, après avoir été soumis à une modulation de trajet optique, sur la première surface, ou d'émission d'un signal optique émis depuis la première surface, après avoir été soumis à une modulation de trajet optique, vers le doigt humain.
(ZH) 一种芯片封装结构、方法和终端设备,能够降低封装的厚度和尺寸,该芯片封装结构(10)包括:光学传感芯片(11),包括第一表面(111)和第二表面(112),第一表面设置有第一焊盘(13),第二表面设置有连接端(15),第一焊盘电连接至连接端,连接端用于芯片封装结构与外界的电连接;光路调制结构(12),设置在第一表面的上方,用于将从人体手指反射的光信号进行光路调制后入射到第一表面,或将从第一表面出射的光信号进行光路调制后出射到人体手指。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)