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1. (WO2018223100) SYSTEM ON A CHIP WITH CUSTOMIZED DATA FLOW ARCHITECTURE
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Pub. No.: WO/2018/223100 International Application No.: PCT/US2018/035754
Publication Date: 06.12.2018 International Filing Date: 01.06.2018
IPC:
G06F 13/24 (2006.01) ,G06F 1/24 (2006.01) ,G06F 1/26 (2006.01) ,G06F 13/00 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
20
for access to input/output bus
24
using interrupt
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
24
Resetting means
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Applicants:
LUKAS, Christopher J. [US/US]; US
CALHOUN, Benton H. [US/US]; US
YAHYA, Farah B. [US/US]; US
UNIVERSITY OF VIRGINIA PATENT FOUNDATION [US/US]; 722 Preston Ave., Suite 107 Charlottesville, Virginia 22903, US
Inventors:
LUKAS, Christopher J.; US
CALHOUN, Benton H.; US
YAHYA, Farah B.; US
Agent:
VILLENEUVE, Joseph M.; US
Priority Data:
62/513,54601.06.2017US
Title (EN) SYSTEM ON A CHIP WITH CUSTOMIZED DATA FLOW ARCHITECTURE
(FR) SYSTÈME SUR PUCE À ARCHITECTURE DE FLUX DE DONNÉES PERSONNALISÉE
Abstract:
(EN) A system-on-a-chip (SoC) comprises a power supply circuit coupled to an energy harvesting transducer and configured to operate using energy from the energy harvesting transducer; a microcontroller coupled to a system bus of the SoC; an interface configured to communicate with the microcontroller via the system bus of the SoC, the interface configured to generate data upon occurrence of an event; and a computation accelerator configured to establish, based on an energy consumption level of the SoC, a data path between the interface and the computation accelerator that at least partially bypasses the system bus such that the data is transmitted to the computation accelerator via the data path.
(FR) L'invention concerne un système sur puce (SoC) comprenant un circuit d'alimentation électrique connecté à un transducteur de collecte d'énergie et configuré pour fonctionner en utilisant l'énergie en provenance du transducteur de collecte d'énergie ; un microcontrôleur connecté à un bus système du SoC ; une interface configurée pour communiquer avec le microcontrôleur par le biais du bus système du SoC, l'interface étant configurée pour générer des données lors de la survenance d'un événement ; et un accélérateur de calcul configuré pour établir, sur la base d'un niveau de consommation d'énergie du SoC, un chemin de données entre l'interface et l'accélérateur de calcul qui contourne au moins partiellement le bus système de telle sorte que les données sont transmises à l'accélérateur de calcul par le biais du chemin de données.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)