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1. (WO2018222915) TWO-DIMENSIONAL PATTERNING OF INTEGRATED CIRCUIT LAYER BY TILTED ION IMPLANTATION
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/222915 International Application No.: PCT/US2018/035461
Publication Date: 06.12.2018 International Filing Date: 31.05.2018
IPC:
H01L 21/027 (2006.01) ,H01L 21/265 (2006.01) ,H01L 21/033 (2006.01) ,H01L 21/02 (2006.01) ,G03F 7/20 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
263
with high-energy radiation
265
producing ion implantation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
033
comprising inorganic layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
7
Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
20
Exposure; Apparatus therefor
Applicants:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA [US/US]; 1111 Franklin Street 12th Floor Oakland, California 94607-5200, US
Inventors:
LIU, Tsu-Jae King; US
DING, Fei; US
WU, Yi-Ting; US
Agent:
DALEY, Henry J.; US
Priority Data:
62/513,10431.05.2017US
Title (EN) TWO-DIMENSIONAL PATTERNING OF INTEGRATED CIRCUIT LAYER BY TILTED ION IMPLANTATION
(FR) FORMATION DE MOTIF BIDIMENSIONNEL DE COUCHE DE CIRCUIT INTÉGRÉ PAR IMPLANTATION IONIQUE INCLINÉE
Abstract:
(EN) A method of producing a micro-device or a nano-device having at least one layer with a sub-lithographic two-dimensional pattern is described herein. The method includes providing a substrate comprising a substructure and a hard mask layer formed on the substructure; performing a plurality of sequential photolithographic and tilted ion implantation processes to produce a pattern of ion implanted regions in the hard mask layer; selectively etching at least one of the ion implanted regions in the hard mask layer to expose the substructure to produce a two-dimensional pattern in the hard mask layer; and selectively etching the substructure of the substrate in exposed regions to transfer the two-dimensional pattern in the hard mask layer to the substructure of the substrate so as to produce a sub-lithographic two-dimensional structure therein.
(FR) L'invention concerne un procédé de production d'un micro-dispositif ou d'un nano-dispositif ayant au moins une couche avec un motif bidimensionnel sous-lithographique. Le procédé consiste à : fournir un substrat comprenant une sous-structure et une couche de masque dur formée sur la sous-structure; réaliser une pluralité de procédés de photolithographie séquentielle et d'implantation ionique inclinée pour produire un motif de régions à implantation ionique dans la couche de masque dur; graver sélectivement au moins une des régions à implantation ionique dans la couche de masque dur pour exposer la sous-structure afin de produire un motif bidimensionnel dans la couche de masque dur; et graver sélectivement la sous-structure du substrat dans des régions exposées pour transférer le motif bidimensionnel dans la couche de masque dur à la sous-structure du substrat de façon à produire une structure bidimensionnelle sous-lithographique à l'intérieur de celle-ci.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)