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1. (WO2018222641) MID-CYCLE ADJUSTMENT OF INTERNAL CLOCK SIGNAL TIMING

Pub. No.:    WO/2018/222641    International Application No.:    PCT/US2018/035009
Publication Date: Fri Dec 07 00:59:59 CET 2018 International Filing Date: Thu May 31 01:59:59 CEST 2018
IPC: H03L 7/18
G06F 13/42
Applicants: TEXAS INSTRUMENTS INCORPORATED
TEXAS INSTRUMENTS JAPAN LIMITED
Inventors: SESHADRI, Anand
MCADAMS, Hugh, P.
Title: MID-CYCLE ADJUSTMENT OF INTERNAL CLOCK SIGNAL TIMING
Abstract:
Changes in operating conditions, like voltage or temperature, can cause the frequency of an internal clock signal to change and negatively affect device operation. In one embodiment, a method of controlling internal clock frequency of a device includes counting a number of clock cycles of the internal clock signal relative to a current period of a system clock signal to determine a current mid-cycle count of clock cycles (102). When the current mid-cycle count differs from a calibrated mid-cycle count by more than a tolerable amount (110), a second clock signal of the clock signals is selected as the internal clock signal (112, 114).