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1. (WO2018222404) SMALL VIAS IN A POLYMER LAYER DISPOSED ON A SUBSTRATE
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Pub. No.: WO/2018/222404 International Application No.: PCT/US2018/033189
Publication Date: 06.12.2018 International Filing Date: 17.05.2018
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
APPLIED MATERIALS, INC. [US/US]; 3050 Bowers Avenue Santa Clara, California 95054, US
Inventors:
GU, Yu; SG
SEE, Guan Huei; SG
SUNDARRAJAN, Arvind; SG
Agent:
TABOADA, Alan; US
MOSER, JR., Raymond R.; US
LINARDAKIS, Leonard P.; US
Priority Data:
15/664,95431.07.2017US
62/514,00001.06.2017US
Title (EN) SMALL VIAS IN A POLYMER LAYER DISPOSED ON A SUBSTRATE
(FR) PETITS TROUS D'INTERCONNEXION DANS UNE COUCHE POLYMÈRE DISPOSÉE SUR UN SUBSTRAT
Abstract:
(EN) Embodiments of methods for creating small via polymer openings on a substrate are provided herein. In some embodiments, methods of processing a substrate include depositing a polymer layer atop the substrate to cover an exposed conductive layer on the substrate; curing the polymer layer; forming a patterned masking layer atop the cured polymer layer; etching an exposed portion of the polymer layer through the patterned masking layer to form a via through the polymer layer to a top surface of the conductive layer; and removing the patterned masking layer.
(FR) La présente invention concerne des modes de réalisation de procédés de création de petits trous d'interconnexion à travers des ouvertures polymères sur un substrat. Selon certains modes de réalisation, des procédés de traitement d'un substrat comprennent le dépôt d'une couche de polymère au-dessus du substrat pour recouvrir une couche conductrice exposée sur le substrat; le durcissement de la couche de polymère; la formation d'une couche de masquage à motifs au-dessus de la couche de polymère durcie; la gravure d'une partie exposée de la couche de polymère à travers la couche de masquage à motifs pour former un trou d'interconnexion à travers la couche de polymère sur une surface supérieure de la couche conductrice; et le retrait de la couche de masquage à motifs.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)