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1. (WO2018221294) ACTIVE MATRIX SUBSTRATE AND METHOD OF MANUFACTURING SAME
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Pub. No.: WO/2018/221294 International Application No.: PCT/JP2018/019489
Publication Date: 06.12.2018 International Filing Date: 21.05.2018
IPC:
H01L 21/336 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 27/088 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
松木薗 広志 MATSUKIZONO Hiroshi; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2017-10783631.05.2017JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND METHOD OF MANUFACTURING SAME
(FR) SUBSTRAT MATRICIEL ACTIF ET SON PROCÉDÉ DE FABRICATION
(JA) アクティブマトリクス基板およびその製造方法
Abstract:
(EN) An active matrix substrate according to an embodiment of the present invention is provided with: a substrate; a plurality of first TFTs supported by the substrate and provided in a non-display region; and a peripheral circuit including the plurality of first TFTs. Each of the first TFTs includes: a first gate electrode provided on the substrate; a first gate insulating layer covering the first gate electrode; a first oxide semiconductor layer facing the first gate electrode with the first gate insulating layer therebetween; and a first source electrode and a first drain electrode which are respectively connected to a source contact region and a drain contact region of the first oxide semiconductor layer. Each of the first TFTs has a bottom contact structure. The thickness of a first region of the first gate insulating layer is smaller than the thickness of a second region of the first gate insulating layer, wherein said first region overlaps a channel region, and said second region overlaps the source contact region and the drain contact region.
(FR) Un substrat matriciel actif selon un mode de réalisation de la présente invention comporte : un substrat, une pluralité de premiers TFT supportés par le substrat et disposés dans une région de non-affichage, et un circuit périphérique contenant la pluralité de premiers TFT. Chacun des premiers TFT comprend : une première électrode de grille disposée sur le substrat; une première couche d'isolation de grille recouvrant la première électrode de grille; une première couche semi-conductrice d'oxyde faisant face à la première électrode de grille avec la première couche d'isolation de grille entre celles-ci; et une première électrode de source et une première électrode de drain qui sont respectivement connectées à une région de contact de source et à une région de contact de drain de la première couche semi-conductrice d'oxyde. Chacun des premiers TFT a une structure de contact inférieure. L'épaisseur d'une première région de la première couche d'isolation de grille est inférieure à l'épaisseur d'une seconde région de la première couche d'isolation de grille, ladite première région chevauchant une région de canal, et ladite seconde région chevauchant la région de contact de source et la région de contact de drain.
(JA) 本発明の実施形態によるアクティブマトリクス基板は、基板と、基板に支持され非表示領域に設けられた複数の第1TFTと、複数の第1TFTを含む周辺回路とを備える。各第1TFTは、基板上に設けられた第1ゲート電極と、第1ゲート電極を覆う第1ゲート絶縁層と、第1ゲート絶縁層を介して第1ゲート電極に対向する第1酸化物半導体層と、第1酸化物半導体層のソースコンタクト領域およびドレインコンタクト領域に接続された第1ソース電極および第1ドレイン電極とを有する。各第1TFTは、ボトムコンタクト構造を有する。第1ゲート絶縁層の、チャネル領域に重なる第1領域の厚さは、第1ゲート絶縁層の、ソースコンタクト領域およびドレインコンタクト領域に重なる第2領域の厚さよりも小さい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)