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1. (WO2018220998) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/220998 International Application No.: PCT/JP2018/014411
Publication Date: 06.12.2018 International Filing Date: 04.04.2018
IPC:
H01L 21/60 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
澤井 敬一 SAWAI, Keiichi; --
Agent:
山尾 憲人 YAMAO, Norihito; JP
山崎 敏行 YAMASAKI, Toshiyuki; JP
Priority Data:
2017-10703530.05.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体装置および半導体装置の製造方法
Abstract:
(EN) Provided is a semiconductor device comprising a first semiconductor chip (10) and a second semiconductor chip (20) that are disposed so as to face each other. The first semiconductor chip (10) has a first connection part (13) provided in a first hole (122), the second semiconductor chip (20) has a conductive second connection part (23) constituted of recessed metal films formed on the surface of a second electrode part (21), the side face of a second hole (222), and the surface of a second protective film (22). A first electrode part (11) and the second electrode part (21) are electrically connected to each other through the first connection part (13) and the second connection part (23).
(FR) L'invention concerne un dispositif à semi-conducteurs comprenant une première puce semi-conductrice (10) et une seconde puce semi-conductrice (20) qui sont disposées de manière l'une en face de l'autre. La première puce semi-conductrice (10) comporte une première partie de connexion (13) disposée dans un premier trou (122), la seconde puce semi-conductrice (20) comporte une seconde partie de connexion conductrice (23) constituée de films métalliques évidés formés sur la surface d'une seconde partie d'électrode (21), sur la face latérale d'un second trou (222), et sur la surface d'un second film de protection (22). Une première partie d'électrode (11) et la seconde partie d'électrode (21) sont électriquement connectées l'une à l'autre par l'intermédiaire de la première partie de connexion (13) et de la seconde partie de connexion (23).
(JA) 半導体装置が、相互に対向するように配置された第1半導体チップ(10)および第2半導体チップ(20)を備える。第1半導体チップ(10)が、第1孔部(122)に設けられた第1接続部(13)を有し、第2半導体チップ(20)が、第2電極部(21)の表面、第2孔部(222)の側面、および、第2保護膜(22)の表面に形成された凹状金属膜で構成されている導電性の第2接続部(23)を有している。第1電極部(11)と第2電極部(21)とが、第1接続部(13)および第2接続部(23)を介して電気的に接続されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)