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1. (WO2018220823) PRINTED CIRCUIT BOARD
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Pub. No.: WO/2018/220823 International Application No.: PCT/JP2017/020622
Publication Date: 06.12.2018 International Filing Date: 02.06.2017
IPC:
H05K 3/46 (2006.01) ,H05K 1/02 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
酒井 あゆみ SAKAI, Ayumi; JP
中本 藤之 NAKAMOTO, Fujiyuki; JP
佐々木 雄一 SASAKI, Yuichi; JP
岡 尚人 OKA, Naoto; JP
大橋 英征 OHASHI, Hideyuki; JP
Agent:
田澤 英昭 TAZAWA, Hideaki; JP
濱田 初音 HAMADA, Hatsune; JP
中島 成 NAKASHIMA, Nari; JP
坂元 辰哉 SAKAMOTO, Tatsuya; JP
辻岡 将昭 TSUJIOKA, Masaaki; JP
井上 和真 INOUE, Kazuma; JP
Priority Data:
Title (EN) PRINTED CIRCUIT BOARD
(FR) CARTE DE CIRCUIT IMPRIMÉ
(JA) プリント回路基板
Abstract:
(EN) In the present invention, a first capacitance C1 exists between a ground layer (3) and a first connection conductor (21) and first component (31). A second capacitance C2 exists between the ground layer (3) and a second connection conductor (22) and second component (32). The length of a first conductor (11) and the length of a second conductor (12) are each adjusted in accordance with the difference ΔC between the first capacitance C1 and the second capacitance C2.
(FR) Dans la présente invention, une première capacité C1 existe entre une couche de masse (3) et un premier conducteur de connexion (21) et un premier composant (31). Une seconde capacité C2 existe entre la couche de masse (3) et un second conducteur de connexion (22) et le second composant (32). La longueur d'un premier conducteur (11) et la longueur d'un second conducteur (12) sont chacune ajustées en fonction de la différence ΔC entre la première capacité C1 et la seconde capacité C2.
(JA) 第1の接続導体(21)及び第1の部品(31)と、グラウンド層(3)との間には第1の静電容量Cが存在し、第2の接続導体(22)及び第2の部品(32)と、グラウンド層(3)との間には第2の静電容量Cが存在しており、第1の静電容量Cと第2の静電容量Cとの差分ΔCに応じて、第1の導体(11)の長さ及び第2の導体(12)の長さがそれぞれ調整されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)